TSV integration on 20nm logic Si: 3D assembly and reliability results

Abstract

Each new technology node brings new design and technology challenges making it harder to maintain Moore's law in a cost effective way. Maintaining cost effectiveness is becoming a major challenge for IDMs, fabless companies and foundries. 3D/2.5D technologies offer some unique advantages over traditional scaling such as higher power efficiency, higher bandwidth and heterogeneous integration which can arguably lower design complexity and manufacturing cost. While advantages of 3D ICs are well known, adoption of this technology has been shifting out due to several technological challenges and manufacturing supply chain concerns. In this paper, 3D packages are realized by stacking mechanical Wide IO memory onto a 20nm low power mobile logic die with through silicon vias (TSVs). This architecture is very promising for mobile application as it can provide lower power consumption, higher bandwidth and faster communication between memory and logic with a smaller form factor. Various technical challenges that were addressed while building a 3D package along with its process and reliability results, both wafer level and package level, are discussed in this paper.