Two 0.8 V, Highly Reliable RHBD 10T and 12T SRAM Cells for Aerospace Applications

Abstract

Aggressive scaling of CMOS technologies requires to pay attention to the reliability issues of circuits. This paper presents two highly reliable RHBD 10T and 12T SRAM cells, which can protect against single-node upsets (SNUs) and double-node upsets (DNUs). The 10T cell mainly consists of two cross-coupled input-split inverters and the cell can robustly keep stored values through a feedback mechanism among its internal nodes. It also has a low cost in terms of area and power consumption, since it uses only a few transistors. Based on the 10T cell, a 12T cell is proposed that uses four parallel access transistors. The 12T cell has a reduced read/write access time with the same soft error tolerance when compared to the 10T cell. Simulation results demonstrate that the proposed cells can recover from SNUs and a part of DNUs. Moreover, compared with the state-of-the-art hardened SRAM cells, the proposed 10T cell can save 28.59% write access time, 55.83% read access time, and 4.46% power dissipation at the cost of 4.04% silicon area on average.

A comprehensive review and side channel attack analysis on radiation-tolerant SRAM cells for aerospace, terrestrial and nuclear applications

“…Aibin Yan et al, 2023 in [56] designed two radiation tolerant cell HRHS18T and HRHS18T EV consisting of eighteen transistors (six NMOSs, six PMOSs and six access transistors) having six storage nodes. In HRHS18T design, the author connected the gate of six NMOS pull-down transistors and six pull-up transistors to the storage nodes and the gate terminal of the six access transistors are attached to the word line.…”