Ultra-Low-Voltage Inverter-Based Amplifier with Novel Common-Mode Stabilization Loop

Manfredini, Giuseppe; Catania, Alessandro; Benvenuti, Lorenzo; Cicalini, Mattia; Piotto, M.; Bruschi, P.

doi:10.3390/electronics9061019

Cited by 27 publications

(28 citation statements)

References 17 publications

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“…Table 3 summarizes the proposed OTA results and compares them to the state-of-art counterparts. The state-of-art OTAs can be categorized by the input terminal of their first stage amplifier block, and can be gate-driven [19,21,24,[27][28][29][30][31] and bulk-driven [18,28,[32][33][34]. Gate-driven OTAs are usually more power-efficient, as the bulk-drain transconductance is a fraction of the gate-drain transconductance, while bulk-driven OTAs have an extended voltage input range, which leads to less signal distortion for larger voltage signal amplitudes.…”

Section: Performance Comparisonmentioning

confidence: 99%

Self-Biased and Supply-Voltage Scalable Inverter-Based Operational Transconductance Amplifier with Improved Composite Transistors

2021

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This paper deals with a single-stage single-ended inverter-based Operational Transconductance Amplifiers (OTA) with improved composite transistors for ultra-low-voltage supplies, while maintaining a small-area, high power-efficiency and low output signal distortion. The improved composite transistor is a combination of the conventional composite transistor and forward-body-biasing to further increase voltage gain. The impact of the proposed technique on performance is demonstrated through post-layout simulations referring to the TSMC 180 nm technology process. The proposed OTA achieves 54 dB differential voltage gain, 210 Hz gain–bandwidth product for a 10 pF capacitive load, with a power consumption of 273 pW with a 0.3 V power supply, and occupies an area of 1026 μm2. For a 0.6 V voltage supply, the proposed OTA improves its voltage gain to 73 dB, and achieves a 15 kHz gain–bandwidth product with a power consumption of 41 nW.

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Section: Performance Comparisonmentioning

confidence: 99%

Self-Biased and Supply-Voltage Scalable Inverter-Based Operational Transconductance Amplifier with Improved Composite Transistors

2021

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“…The OTA reported in [20] operates with a supply voltage of 1 V and exhibits state of the art small-signal and large-signal figures of merit. Unfortunately, most of these conventional amplifier topologies are not suited for applications requiring supply voltages lower than 0.5 V, and inverter-based [21][22][23][24][25][26] and pseudo-differential [27,28] architectures are preferred. However, an aggressive supply voltage scaling severely limits the swing of the control voltage, thus strongly limiting the effectiveness of body bias approaches to set the bias or the common mode current.…”

Section: Introductionmentioning

confidence: 99%

A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers

Centurelli

Sala

Monsurrò

et al. 2022

JLPEA

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In this paper, we introduce a novel tree-based architecture which allows the implementation of Ultra-Low-Voltage (ULV) amplifiers. The architecture exploits a body-driven input stage to guarantee a rail-to-rail input common mode range and body-diode loading to avoid Miller compensation, thanks to the absence of high-impedance internal nodes. The tree-based structure improves the CMRR of the proposed amplifier with respect to the conventional OTA architectures and allows achievement of a reasonable CMRR even at supply voltages as low as 0.3 V and without tail current generators which cannot be used in ULV circuits. The bias currents and the static output voltages of all the stages implementing the architecture are accurately set through the gate terminals of biasing transistors in order to guarantee good robustness against PVT variations. The proposed architecture and the implementing stages are investigated from an analytical point of view and design equations for the main performance metrics are presented to provide insight into circuit behavior. A 0.3 V supply voltage, subthreshold, ultra-low-power (ULP) OTA, based on the proposed tree-based architecture, was designed in a commercial 130 nm CMOS process. Simulation results show a dc gain higher than 52 dB with a gain-bandwidth product of about 35 kHz and reasonable values of CMRR and PSRR, even at such low supply voltages and considering mismatches. The power consumption is as low as 21.89 nW and state-of-the-art small-signal and large-signal FoMs are achieved. Extensive parametric and Monte Carlo simulations show the robustness of the proposed circuit to PVT variations and mismatch. These results confirm that the proposed OTA is a good candidate to implement ULV, ULP, high performance analog building blocks for directly harvested IoT nodes.

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“…In this ultra-constrained scenario several high performance OTAs which exploit body-driven gate-biased architectures have been presented in the recent literature [3]- [5]. In detail, the usage of the body-driven approach has resulted in a plenty of topologies which exhibit state-of-the-art performances, both in terms of small signal and large signal figures of merit, and good robustness with respect to process, supply voltage and temperature (PVT) variations [3], [6], [7]. However, such OTAs have to be designed and routed manually and very often result in huge area occupation, due to the fact that separate wells are mandatory to implement body-driven architectures.…”

Section: Introductionmentioning

confidence: 99%

A Novel Differential to Single-Ended Converter for Ultra-Low-Voltage Inverter-Based OTAs

2022

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For the design of inverter-based OTAs with differential input and single-ended output, the differential to single-ended (D2S) converter is a key building block. In fact, the performance of the D2S strongly affects the overall common-mode rejection ratio (CMRR) and input common-mode range (ICMR) of the whole OTA. In recent literature, inverter-based OTAs rely on a D2S topology based on an inverter driving another inverter with the input and output tight together which behaves as a "diode" connected device to implement a voltage gain approximately equal to −1. However, since this approach is based on the matching of the inverters, the performance of this D2S results sensitive to PVT variations if the bias point of the inverters is not properly stabilized. In this paper we present a novel topology of inverterbased D2S converter, exploiting an auxiliary, standard-cell-based, error amplifier and a local feedback loop. The proposed D2S, compared to the conventional one, exhibits higher CMRR, improved ICMR and better robustness with respect to PVT variations. We present also an ULV, standard-cell-based OTA, which exploits the proposed D2S converter and shows excellent performance figures of merit with low area footprint.

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Ultra-Low-Voltage Inverter-Based Amplifier with Novel Common-Mode Stabilization Loop

Cited by 27 publications

References 17 publications

Self-Biased and Supply-Voltage Scalable Inverter-Based Operational Transconductance Amplifier with Improved Composite Transistors

Self-Biased and Supply-Voltage Scalable Inverter-Based Operational Transconductance Amplifier with Improved Composite Transistors

A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers

A Novel Differential to Single-Ended Converter for Ultra-Low-Voltage Inverter-Based OTAs

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