1992
DOI: 10.1109/16.163462
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Ultra-shallow junction formation using silicide as a diffusion source and low thermal budget

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Cited by 63 publications
(13 citation statements)
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“…Boron diffusion from CoSi 2 into silicon in [3 to 5] can serve as example for the application of (5) and (6). The following parameters were taken from [3 to 5, 7]: annealing temperature T 950 C, Q 5 Â 10 15 cm À2 , R p 6X2 nm, DR p 3X2 nm, d 50 nm, m 0X427, D 1 8X1 Â 10 À12 cm 2 as, D 2 1X43 Â 10 À13 cm 2 as.…”
Section: Resultsmentioning
confidence: 99%
See 1 more Smart Citation
“…Boron diffusion from CoSi 2 into silicon in [3 to 5] can serve as example for the application of (5) and (6). The following parameters were taken from [3 to 5, 7]: annealing temperature T 950 C, Q 5 Â 10 15 cm À2 , R p 6X2 nm, DR p 3X2 nm, d 50 nm, m 0X427, D 1 8X1 Â 10 À12 cm 2 as, D 2 1X43 Â 10 À13 cm 2 as.…”
Section: Resultsmentioning
confidence: 99%
“…Since the dopant diffusion in the silicide layer is very fast relative to dopant diffusion in silicon, it was usually assumed that the dopant diffusion in the silicide is instantaneous. However, it was indicated [6] that the diffusion anneal required to obtain a given penetration profile has to be adjusted somewhat as a function of the implant energy (or depth) in the silicide. In other words the finite thickness of the silicide layer must be considered.…”
Section: Introductionmentioning
confidence: 99%
“…Several achievements in finding new materials and developing new process for sub-100 nm device manufacturing have been made recently. These processes or materials include the elevated source/drain [29][30][31][32][33], plasma doping with flash or laser annealing [34][35][36][37][38][39][40][41][42][43], NiSi silicide [44][45][46][47][48][49][50][51][52][53][54][55][56], strained Si channel for mobility enhancement [57][58][59][60][61][62][63][64], silicon on insulator (SOI) [65][66][67], three-dimensional structure [68][69][70][71][72][73][74][75] high dielectric constant (high-k) gate insulator …”
Section: Degradation Of Performance With Downscalingmentioning
confidence: 99%
“…[13][14][15] This process still requires a detailed investigation of the dopant diffusion in the Si substrate as a function of the process parameters, but this study cannot be easily performed with the usual profile techniques ͑SIMS and SR͒ because of the roughness of the silicide/Si interface. [13][14][15] This process still requires a detailed investigation of the dopant diffusion in the Si substrate as a function of the process parameters, but this study cannot be easily performed with the usual profile techniques ͑SIMS and SR͒ because of the roughness of the silicide/Si interface.…”
Section: Applications To Device Characterizationmentioning
confidence: 99%