Uniform non-Bernoulli sequences oriented locating method for reliability-critical gates

Xiao, Jie; Shi, Zhanhui; Zhu, Weidong; Jiang, Jianhui; Zhou, Qianwei; Lou, Jungang; Huang, Yina; Ji, Qiou; Sun, Ziwen

doi:10.26599/tst.2019.9010045

Cited by 9 publications

(1 citation statement)

References 7 publications

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“…Existing approaches do not sufficiently consider the use times of the RCA or the non-original input or output times. Xiao et al [15] and Ouyang et al [16] discussed gates and fault tolerant design.…”

Section: Introductionmentioning

confidence: 99%

Efficient scheduling mapping algorithm for row parallel coarse-grained reconfigurable architecture

Chen

Wang

et al. 2021

Tsinghua Sci. Technol.

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Row Parallel Coarse-Grained Reconfigurable Architecture (RPCGRA) has the advantages of maximum parallelism and programmable flexibility. Designing an efficient algorithm to map the diverse applications onto RPCGRA is difficult due to a number of RPCGRA hardware constraints. To solve this problem, the nodes of the data flow graph must be partitioned and scheduled onto the RPCGRA. In this paper, we present a Depth-First Greedy Mapping (DFGM) algorithm that simultaneously considers the communication costs and the use times of the Reconfigurable Cell Array (RCA). Compared with level breadth mapping, the performance of DFGM is better. The percentage of maximum improvement in the use times of RCA is 33% and the percentage of maximum improvement in non-original input and output times is 64.4% (Given Discrete Cosine Transfor 8 (DCT8), and the area of reconfigurable processing unit is 56). Compared with level-based depth mapping, DFGM also obtains the lowest averages of use times of RCA, non-original input and output times, and the reconfigurable time.

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Section: Introductionmentioning

confidence: 99%