1964
DOI: 10.1109/proc.1964.3495
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Unilateral frequency multiplier circuit

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Cited by 5 publications
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“…The work presented here applies this architecture to implement an integrated frequency quadrupler with output frequency of 160 GHz using quasi-vertical GaAs varactors fabricated on thin silicon support membranes. The use of a balanced circuit architecture to realize "unilateral" multipliers that are insensitive to the loading effects of the output stages appears to have been first proposed by Gewartowski in 1964 [94] who later applied this approach to realize a quadrupler with 2.5 W of output power at 6 GHz [95]. The quadrupler presented here makes use of the same basic approach, but differs from that of Gewartowski as it uses a second-stage balanced doubler at the output to generate the fourth harmonic.…”
Section: Quasi-vertical Schottky Diode Multipliersmentioning
confidence: 99%
“…The work presented here applies this architecture to implement an integrated frequency quadrupler with output frequency of 160 GHz using quasi-vertical GaAs varactors fabricated on thin silicon support membranes. The use of a balanced circuit architecture to realize "unilateral" multipliers that are insensitive to the loading effects of the output stages appears to have been first proposed by Gewartowski in 1964 [94] who later applied this approach to realize a quadrupler with 2.5 W of output power at 6 GHz [95]. The quadrupler presented here makes use of the same basic approach, but differs from that of Gewartowski as it uses a second-stage balanced doubler at the output to generate the fourth harmonic.…”
Section: Quasi-vertical Schottky Diode Multipliersmentioning
confidence: 99%