Variation-aware Flip-Flop energy optimization for ultra low voltage operation

Abstract

This paper presents an energy optimization method for a Flip-Flop (FF) circuit in a presence of manufacturing process variation. The optimal FF circuit can be obtained by simultaneously scaling the supply voltage and the transistor size with achieving a specific high yield of the circuit. Lowering the supply voltage is one of the most effective approaches for decreasing the energy consumption of the circuit. However, the increased variation in nano scale semiconductor devices causes a malfunction of FFs especially for the very low voltage operation. Therefore, it is a challenging goal for the nano scale FFs to achieve the high yield and extremely low energy consumption simultaneously. This paper proposes an approximation method for accurately estimating a minimum possible operating voltage (V DDmin ) of FFs with a small number of Monte-Carlo trials. After that, for a given FF, we find a set of optimal supply voltage and the transistor sizes, which minimizes the energy consumption of the FF with achieving the specific high-sigma yield (e.g., 5σ yield). Post layout Monte-Carlo simulation results obtained using a commercial 28 nm process technology model demonstrate that the energy consumption of a FF optimized with our approach can be reduced by 17% at the best case with achieving 5σ yield.