Variation-Tolerant Dynamic Power Management at the System-Level

Chandra, Saumya; Lahiri, Kanishka; Raghunathan, Anand; Dey, Sujit

doi:10.1109/tvlsi.2009.2019803

Cited by 22 publications

(12 citation statements)

References 18 publications

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“…Variation-aware adjustment of hardware operating point, whether in the context of adaptive circuits (e.g., [69]- [71]), adaptive microarchitectures (e.g., [28], [72]- [74]), or softwareassisted hardware power management (e.g., [4], [75], [76]) has been explored extensively in literature. UnO software stack will be cognizant of actuation mechanisms available in hardware and utilize them in an application-aware manner.…”

Section: Adjusting Hardware Operating Pointmentioning

confidence: 99%

Underdesigned and Opportunistic Computing in Presence of Hardware Variability

Gupta

Agarwal

Dolecek

et al. 2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

138

116

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Abstract-Microelectronic circuits exhibit increasing variations in performance, power consumption, and reliability parameters across the manufactured parts and across use of these parts over time in the field. These variations have led to increasing use of overdesign and guardbands in design and test to ensure yield and reliability with respect to a rigid set of datasheet specifications. This paper explores the possibility of constructing computing machines that purposely expose hardware variations to various layers of the system stack including software. This leads to the vision of underdesigned hardware that utilizes a software stack that opportunistically adapts to a sensed or modeled hardware. The envisioned underdesigned and opportunistic computing (UnO) machines face a number of challenges related to the sensing infrastructure and software interfaces that can effectively utilize the sensory data. In this paper, we outline specific sensing mechanisms that we have developed and their potential use in building UnO machines.

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Section: Adjusting Hardware Operating Pointmentioning

confidence: 99%

Underdesigned and Opportunistic Computing in Presence of Hardware Variability

Gupta

Agarwal

Dolecek

et al. 2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

138

116

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“…Therefore, budgeting for the WCET may result in excessive energy consumption. The researchers in [11] and [12] have proposed power management approaches which track the critical path changes and consider the impact of process variations.…”

Section: Introductionmentioning

confidence: 99%

Dynamic Voltage and Frequency Scheduling for Embedded Processors Considering Power/Performance Tradeoffs

Salehi

Samadi

Najibi

et al. 2011

IEEE Trans. VLSI Syst.

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Abstract-An adaptive method to perform dynamic voltage and frequency scheduling (DVFS) for minimizing the energy consumption of microprocessor chips is presented. Instead of using a fixed update interval, the proposed DVFS system makes use of adaptive update intervals for optimal frequency and voltage scheduling. The optimization enables the system to rapidly track the workload changes so as to meet soft real-time deadlines. The technique, which can be realized with very simple hardware, is completely transparent to the application. The results of applying the method to some real application workloads demonstrate considerable power savings and fewer frequency updates compared to DVFS systems based on fixed update intervals.

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“…There have been extensive researches on task scheduling and binding for MPSoC [13], [14], [15], [16], [17], [18], and also MPSoC power management [19], [20], [21], but few of them have addressed process variability.…”

Section: A Related Workmentioning

confidence: 99%

Variation-aware task scheduling and power mode selection for MPSoC power optimization

Momtazpour¹,

Goudarzi²,

Sanaei³

2010

2010 15th CSI International Symposium on Computer Architecture and Digital Systems

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Increasing delay and power variation has become a major challenge to designing high performance Multiprocessor System-On-Chips (MPSoC) in deep sub-micron technologies. As a result, a paradigm shift from deterministic to statistical design methodology at all levels of the design hierarchy is inevitable. In this paper, we propose a static variation-aware task scheduling and power mode selection algorithm for MPSoCs. The proposed algorithm is able to maximize the total power yield of the chip under a given performance yield constraint by searching for the optimal task scheduling and power mode selection policy for a specified multiprocessor platform. Experimental results are gathered by simulating the algorithm with two different statistical analysis methods called Monte Carlo and Event-Reference-Table-based method. We have shown that by considering both leakage and frequency variation during the simultaneous selection of task scheduling and power mode switching policies, our algorithm achieves significant improvement over conventional methods.

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Variation-Tolerant Dynamic Power Management at the System-Level

Cited by 22 publications

References 18 publications

Underdesigned and Opportunistic Computing in Presence of Hardware Variability

Underdesigned and Opportunistic Computing in Presence of Hardware Variability

Dynamic Voltage and Frequency Scheduling for Embedded Processors Considering Power/Performance Tradeoffs

Variation-aware task scheduling and power mode selection for MPSoC power optimization

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