Vectored-Bloom Filter Implemented on FPGA for IP Address Lookup

Byun, Hayoung; Li, Qingling; Lim, Hyesook

doi:10.23919/elinfocom.2019.8706399

Cited by 5 publications

(3 citation statements)

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“…The basic idea of the proposed vectored-Bloom filter (VBF) structure for IP address lookup was briefly introduced in References [31] and [32]. The VBF consists of m multi-bit vectors and each vector comprised of l bits contains an output port.…”

Section: Ip Address Lookup Using a Vectored-bloom Filtermentioning

confidence: 99%

“…Hence, Section 4 is completely a new section compared with Reference [31]. In Reference [32], even though the hardware architecture of the VBF implemented on the FPGA is briefly described, the proposed structure has not been evaluated through a behavior simulation and not been compared with other algorithms. In this paper, we describe our algorithm and the proposed hardware structures in detail and the proposed architecture has been evaluated through both a behavior simulation with C language and a timing simulation with Verilog.…”

Section: Ip Address Lookup Using a Vectored-bloom Filtermentioning

confidence: 99%

“…Hence. the Section 5 is completely a new section and Section 6 is largely extended compared with Reference [32].…”

Section: Ip Address Lookup Using a Vectored-bloom Filtermentioning

confidence: 99%

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Vectored-Bloom Filter for IP Address Lookup: Algorithm and Hardware Architectures

Byun

Lim

2019

Applied Sciences

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The Internet Protocol (IP) address lookup is one of the most challenging tasks for Internet routers, since it requires to perform packet forwarding at wire-speed for tens of millions of incomming packets per second. Efficient IP address lookup algorithms have been widely studied to satisfy this requirement. Among them, Bloom filter-based approach is attractive in providing high performance. This paper proposes a high-speed and flexible architecture based on a vectored-Bloom filter (VBF), which is a space-efficient data structure that can be stored in a fast on-chip memory. An off-chip hash table is infrequently accessed, only when the VBF fails to provide address lookup results. The proposed architecture has been evaluated through both a behavior simulation with C language and a timing simulation with Verilog. The hardware implementation result shows that the proposed architecture can achieve the throughput of 5 million packets per second in a field programmable gate array (FPGA) operated at 100 MHz.

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Section: Ip Address Lookup Using a Vectored-bloom Filtermentioning

confidence: 99%

Section: Ip Address Lookup Using a Vectored-bloom Filtermentioning

confidence: 99%