Verilog and VHDL

Bergé, Jean-Michel; Fonkoua, Alain; Maginot, Serge; Rouillard, Jacques

doi:10.1007/978-1-4615-3498-3_9

Cited by 4 publications

(2 citation statements)

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“…Hardware resource Description Languages (HDLs) are essential tools to build an architecture simulator, and to build an efficient simulator we must use a powerful, accurate and appropriate resource description model. While classical HDLs, like Verilog and VHDL [152], are very good at describing detailed hardware characteristics and behaviors (such as timing behavior), they are generally inadequate for expressing the higher-level abstractions required for (today and) future large and complex micro-architectural architecture designs.…”

Section: Speed Vs Accuracymentioning

confidence: 99%

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

Zarrin

Aguiar

Barraca

2017

Simulation Modelling Practice and Theory

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This is the accepted version of the paper.This version of the publication may differ from the final published version. Permanent repository link AbstractThe architecture design of peta-scale computing systems is complex and presents lots of difficulties to designs, as current tools lack support for relevant features of future scenarios. Novel systems must be designed with great care and tools, such as manycore architecture simulators, must be adapted accordingly. However, current simulation tools are very slow, often specific-purposeoriented, suffer from various issues and are rarely able to simulate thousands of cores. The emergence of peta-scale systems and the upcoming manycore era brings nevertheless new challenges to computing systems and architectures, adding further difficulties and requirements on the development of the corresponding simulators. Furthermore, the design of architecture simulators for manycore systems involve methods and techniques from various interdisciplinary research areas, which in turn brings more challenges in different aspects. As system complexity grows, the growth of the simulation capacity is being outpaced (reaching the so called simulation wall). In this paper, we present the challenges for simulating future large scale manycore environments, and we investigate the adequacy of current modeling and simulation tools, methodologies and techniques. The aim of this work is to highlight how current approaches can best deal with the identified problems, smoothing the challenges of research in future peta-scale systems.

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Section: Speed Vs Accuracymentioning

confidence: 99%

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

Zarrin

Aguiar

Barraca

2017

Simulation Modelling Practice and Theory

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“…VHDL Designer's Reference [1] was the first comprehensive report to compare VHDL and Verilog-HDL, but it was a descriptive explanation not based on a formal method. Gordon [14] appealed the necessity of formal analysis.…”

Section: Introductionmentioning

confidence: 99%

A formal semantics for Verilog-VHDL simulation interoperability by abstract state machine

Sasaki

1999

Proceedings of the Conference on Design, Automation and Test in Europe

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A formal semantic analysis for Verilog-HDL and VHDL is provided in order to give the simulation model especially focusing on signal scheduling and timing control mechanism. Our semantics is faithful to LRM and is expected to become a coherent first step for a future semantic interoperability analysis on multisemantic-domain such as Verilog-AMS and VHDL-AMS. By ignoring the differences of the two simulation cycles, we can use the common semantic functions and the common simulation cycle.

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Automatic Test Case Generation for Prime Field Elliptic Curve Cryptographic Circuits

Gupt

Kshirsagar

Sullivan

et al. 2021

2021 IEEE 17th International Colloquium on Signal Processing &Amp; Its Applications (CSPA)

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Verilog and VHDL

Cited by 4 publications

References 0 publications

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

A formal semantics for Verilog-VHDL simulation interoperability by abstract state machine

Automatic Test Case Generation for Prime Field Elliptic Curve Cryptographic Circuits

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