Versatile firmware for the Common Readout Unit (CRU) of the ALICE experiment at the LHC

Bourrion, O.; Bouvier, J.; Costa, F.; David, E.; Imrek, J.; Nguyen, Thi-Huyen; Mukherjee, Sanjoy

doi:10.1088/1748-0221/16/05/p05019

Cited by 10 publications

(12 citation statements)

References 7 publications

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“…Another example is the firmware for the CRU board [6] used by the ALICE experiment at LHC at CERN. It uses a round-robin scanning of the output of FEE links (see [6], figure 8).…”

Section: High Speed Pollingmentioning

confidence: 99%

“…Another example is the firmware for the CRU board [6] used by the ALICE experiment at LHC at CERN. It uses a round-robin scanning of the output of FEE links (see [6], figure 8). Then only the valid data are packed into the 256-bit wide FIFO, delivering the data to PCIe.…”

Section: High Speed Pollingmentioning

confidence: 99%

“…swap(&l0 [4],&l0[5],&l1 [2],&l1 [6],isw & (1<<2)); swap(&l0 [6],&l0 [7],&l1 [3],&l1 [7],isw & (1<<3)); //2nd layer of switches swap(&l1[0],&l1 [1],&l2[0],&l2 [2],isw & (1<<4)); swap(&l1 [2],&l1 [3],&l2 [1],&l2 [3],isw & (1<<5)); swap(&l1 [4],&l1[5],&l2 [4],&l2 [6],isw & (1<<6)); swap(&l1 [6],&l1 [7],&l2[5],&l2 [7],isw & (1<<7)); //3rd layer of switches swap(&l2[0],&l2 [1],&l3[0],&l3 [2],isw & (1<<8)); swap(&l2 [2],&l2 [3],&l3 [1],&l3 [3],isw & (1<<9)); swap(&l2 [4],&l2[5],&l3 [4],&l3 [6],isw & (1<<10)); swap(&l2 [6],&l2 [7],&l3[5],&l3 [7],isw & (1<<11)); //4th layer of switches swap(&l3[0],&l3 [1],&l4[0],&l4 [2],isw & (1<<12)); swap(&l3 [2],&l3 [3],&l4 [4],&l4 [6],isw & (1<<13)); swap(&l3 [4],&l3[5],&l4 [1],&l4 [3],isw & (1<<14)); swap(&l3 [6],&l3…”

Section: Calculation Of the Future Occupancymentioning

confidence: 99%

“…//1st layer of switches swap(&l0[0],&l0 [1],&l1[0],&l1 [4],isw & (1<<0)); swap(&l0 [2],&l0 [3],&l1 [1],&l1[5],isw & (1<<1)); swap(&l0 [4],&l0[5],&l1 [2],&l1 [6],isw & (1<<2)); swap(&l0 [6],&l0 [7],&l1 [3],&l1 [7],isw & (1<<3)); //2nd layer of switches swap(&l1[0],&l1 [1],&l2[0],&l2 [2],isw & (1<<4)); swap(&l1 [2],&l1 [3],&l2 [1],&l2 [3],isw & (1<<5)); swap(&l1 [4],&l1[5],&l2 [4],&l2 [6],isw & (1<<6)); swap(&l1 [6],&l1 [7],&l2[5],&l2 [7],isw & (1<<7)); //3rd layer of switches swap(&l2[0],&l2 [1],&l3[0],&l3 [4],isw & (1<<8)); swap(&l2 [2],&l2 [3],&l3 [2],&l3 [6],isw & (1<<9)); swap(&l2 [4],&l2[5],&l3 [1],&l3[5],isw & (1<<10)); swap(&l2 [6],&l2 [7],&l3 [3],&l3 [7],isw & (1<<11)); fprintf(fout,"%8.8x:%d%d%d%d%d%d%d%d \n " ,isw, (int)l3[0],(int)l3 [1],(int)l3 [2],(int)l3 [3], (int)l3 [4],(int)l3[5],(int)l3 [6],(int)l3 …”

Section: Calculation Of the Future Occupancymentioning

confidence: 99%

See 3 more Smart Citations

Beneš Network Based Efficient Data Concentrator for Triggerless Data Acquisition Systems

Gumiński¹,

Kruszewski²,

Zabołotny³

et al. 2023

Preprint

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The concentration of data from multiple links to a single output is an essential task performed by High-Energy Physics (HEP) Data Acquisition Systems (DAQs). At high and varying data rates combined with the large width of the concentrator’s output interface, this task is non-trivial. This paper presents a concentrator based on the Bene&scaron; network, which provides efficient concentration without using a high-frequency clock internally. It warrants that empty data are eliminated and does not disturb the data time-ordering if the data rates significantly differ between inputs. Additionally, it is well suited to FPGA implementation. It is based on simple data-routing primitives and may be fully pipelined.

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“…Another example is the firmware for the CRU board [6] used by the ALICE experiment at LHC at CERN. It uses a round-robin scanning of the output of FEE links (see [6], figure 8).…”

Section: High Speed Pollingmentioning

confidence: 99%

Section: High Speed Pollingmentioning

confidence: 99%

Section: Calculation Of the Future Occupancymentioning

confidence: 99%

Section: Calculation Of the Future Occupancymentioning

confidence: 99%

See 2 more Smart Citations

Beneš Network Based Efficient Data Concentrator for Triggerless Data Acquisition Systems

Gumiński¹,

Kruszewski²,

Zabołotny³

et al. 2023

Preprint

View full text Add to dashboard Cite

show abstract

“…This enables the reuse of DDL-enabled hardware from Run2 for a few detectors that would not benefit from higher throughput capabilities. The CRU uses the GBT protocol [9] for its readout links and its firmware is under active development [10].…”

Section: A Crorcmentioning

confidence: 99%

The ReadoutCard userspace driver for the new ALICE $O^2$ computing system

Alexopoulos,

Costa

2020

Preprint

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The ALICE (A Large Ion Collider Experiment) experiment focuses on the study of the quark-gluon plasma as a product of heavy-ion collisions at the CERN LHC (Large Hadron Collider). During the Long Shutdown 2 of the LHC in 2019-2020, a major upgrade is underway in order to cope with a hundredfold input data rate increase with peaks of up to 3.5 TB/s. This upgrade includes the new Online-Offline computing system called O 2 .The O 2 readout chain runs on commodity Linux servers equipped with custom PCIe FPGA-based readout cards; the PCIe v3 x16, Intel Arria 10-based CRU (Common Readout Unit) and the PCIe v2 x8, Xilinx Vertex 6-based CRORC (Common Read-Out Receiver Card). Access to the cards is provided through the O 2 ReadoutCard userspace driver which handles synchronization and communication for DMA transfers, provides BAR access, and facilitates card configuration and monitoring. The ReadoutCard driver is the lowest-level interface to the readout cards within O 2 and is in use by all central systems and detector teams of the ALICE experiment.This communication presents the architecture of the driver, and the suite of tools used for card configuration and monitoring. It also discusses its interaction with the tangent subsystems within the O 2 framework.

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AliECS: A New Experiment Control System for the ALICE Experiment

Mrnjavac,

Alexopoulos,

Chibante Barroso

et al. 2024

EPJ Web of Conf.

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The ALICE Experiment at CERN’s Large Hadron Collider (LHC) has undergone a major upgrade during LHC Long Shutdown 2 in 2019-2021, which includes a new computing system called O2 (Online-Offline). To ensure the efficient operation of the upgraded experiment and of its newly designed computing system, a reliable, high performance, full-featured experiment control system has also been developed and deployed at LHC Point 2. The ALICE Experiment Control System (AliECS) is a microservices-oriented system based on state-of-the-art cluster management technologies that emerged recently in the distributed and high-performance computing ecosystem. It is designed, developed and maintained as a comprehensive solution and single entry point for control of experiment data acquisition (up to 3.5 TB/s) and processing. This communication describes the AliECS architecture by providing an in-depth overview of the system’s components, interfaces, features, and design elements, as well as its performance. It also reports on the experience with AliECS during the first year of ALICE Run 3 data taking with LHC beam, including integration and operational challenges, and lessons learned from real-world use.

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Versatile firmware for the Common Readout Unit (CRU) of the ALICE experiment at the LHC

Cited by 10 publications

References 7 publications

Beneš Network Based Efficient Data Concentrator for Triggerless Data Acquisition Systems

Beneš Network Based Efficient Data Concentrator for Triggerless Data Acquisition Systems

The ReadoutCard userspace driver for the new ALICE $O^2$ computing system

AliECS: A New Experiment Control System for the ALICE Experiment

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