Vision Chip Architecture for Detecting Line of Sight Including Saccade

Abstract

SUMMARYRapid eye motion, or so called saccade, is a very quick eye motion which always occurs regardless of our intention. Although the line of sight (LOS) with saccade tracking is expected to be used for a new type of computer-human interface, it is impossible to track it using the conventional video camera, because of its speed which is often up to 600 degrees per second. Vision Chip is an intelligent image sensor which has the photo receptor and the image processing circuitry on a single chip, which can process the acquired image information by keeping its spatial parallelism. It has also the ability of implementing the very compact integrated vision system. In this paper, we describe the vision chip architecture which has the capability of detecting the line of sight from infrared eye image, with the processing speed supporting the saccade tracking. The vision chip described here has the pixel parallel processing architecture, with the node automata for each pixel as image processing. The acquired image is digitized to two flags indicating the Purkinje's image and the pupil by comparators at first. The digitized images are then shrunk, followed by several steps of expanding by node automata located at each pixel. The shrinking process is kept executed until all the pixels disappear, and the pixel disappearing at last indicates the center of the Purkinje's image and the pupil. This disappearing step is detected by the projection circuitry in pixel circuit for fast operation, and the coordinates of the center of the Purkinje's image and the pupil are generated by the simple encoders. We describe the whole architecture of this vision chip, as well as the pixel architecture. We also describe the evaluation of proposed algorithm with numerical simulation, as well as processing speed using FPGA, and improvement in resolution using column parallel architecture. key words: vision chip, line of sight, saccade, pixel parallel processing, automata

Column-Parallel Vision Chip Architecture for High-Resolution Line-of-Sight Detection Including Saccade

“…The authors have indicated that the positions of both the pupil and the Purkinje's image in the infrared eye image can be detected by the following five operation procedures [7].…”

“…The position detection performed by the shrink operations can eliminate these unnecessary areas prior to the detections of the pupil and the Purkinje's image eliminations by appropriate shrink operation rules [7].…”

“…The cell size is 14.3 [µm] × 12. 7 [µm] for the unit of two bits. The width of MEM is also determined to adjust the width of processing element, PE.…”

“…Assuming that the required frame rate for LoS detection including saccade as 500 [Hz] [3], [7], or T of 2 [ms], N as 480 for VGA resolution (640 × 480 pixels), and t t of 1 [µs] for practical image sensors, the required operation frequency, f , for PE, WM, and MEM can be estimated as follows.…”

“…Generally, the image processing in vision chip is performed in pixel parallel manner, and this architecture intrinsically results in low resolution because of pixel circuit size, such as 64 × 64 pixels in [6]. We have already reported a vision chip architecture for LoS detection including saccade in pixel parallel architecture [7], however, the proposed vision chip has the resolution of 16 × 16 pixels in 2.3 mm square chip using 0.35 µm CMOS technology. The low resolution of vision chip is one of the most critical reasons that prevents commercial products of vision chips.…”