VLSI architecture for an object change detector for visual sensors

Aguilar-Ponce, Ruth M.; Tessier, Jared; Baker, A.; Emmela, C.; Das, Jadav Chandra; Tecpanecatl-Xihuitl, J. Luis; Kumar, Ashok; Bayoumi, Magdy

doi:10.1109/sips.2005.1579881

Cited by 3 publications

(3 citation statements)

References 8 publications

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“…It is given as Assume that the number of local decision '1' received from at the fusion center is denoted as , , thus . Based on the property of logarithm, can be given as (13) where (14) Using (13), we can choose the which satisfies (15) Specifically, the value of in (13) can be calculated easily with the shift operation. In the executing process of the above equation, we add a constraint into the search space to reduce the computational complexity.…”

Section: Various Differences Between M and Mmentioning

confidence: 99%

“…In [14], Alippi et al proposed a low-power maximum power point tracker (MPPT) circuit, conveying solar energy into rechargeable batteries, for wireless sensor nodes. Furthermore, Aguilar-Ponce et al proposed a VLSI architecture for Wronskian Change Detector [15] and Goldberg et al proposed a low-power VLSI wake-up detector for the use in an acoustic surveillance sensor network [16]. To our knowledge, ACSFD circuit is the first ASIC implementation for fault-tolerance fusion center and no related state-of-the-art ASIC design exists in the literature.…”

Section: Introductionmentioning

confidence: 99%

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A Low-Cost VLSI Architecture for Fault-Tolerant Fusion Center in Wireless Sensor Networks

Chen

Chang

Wang

2010

IEEE Trans. Circuits Syst. I

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A fault-tolerant distributed decision fusion in the presence of sensor faults via collaborative sensor fault detection (CSFD) was proposed in our previous research [7]. The scheme can identify the faulty nodes efficiently and improve the performance of the decision fusion significantly. It achieves very good performance at the expense of such extensive computations as exponent and multiplication/division in the detecting process. In many real-time WSN applications, the fusion center might be implemented in an ASIC and included in a standalone device. Therefore, a simple and efficient decision fusion scheme requiring lower hardware cost and power consumption is extremely desired. In this paper, we propose the approximated collaborative sensor fault detection (ACSFD) scheme and its VLSI architecture. Given the low circuit complexity, it is suitable for hardware implementation. The ACSFD circuit contains 9265 gates and requires a core size of 368 358 m 2 by using TSMC 0.18 m cell library. It can operate at a clock rate of 102 MHz with a power consumption of 2.516 mW. Simulation results indicate that ACSFD performs better in fault tolerance than the conventional approach.

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Section: Various Differences Between M and Mmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Low-Cost VLSI Architecture for Fault-Tolerant Fusion Center in Wireless Sensor Networks

Chen

Chang

Wang

2010

IEEE Trans. Circuits Syst. I

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“…implementation of motion segmentation, image filtering, or video codec. Some examples are AguilarPonce et al [9] and Fahmy et al [10] that describe the implementation of a motion segmentation algorithm and a high speed median filter, respectively. FPGA implementations of video codecs for MPEG-4 and H.264 are found in Schumacher et al [11] and Kordasiewicz et al [12].…”

Section: Systems Of Todaymentioning

confidence: 99%

An Embedded Real-Time Surveillance System: Implementation and Evaluation

Kristensen

Hedberg

Jiang

et al. 2007

J Sign Process Syst Sign Image Video Technol

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This paper presents the design of an embedded automated digital video surveillance system with real-time performance. Hardware accelerators for video segmentation, morphological operations, labeling and feature extraction are required to achieve the real-time performance while tracking will be handled in software in an embedded processor. By implementing a complete embedded system, bottlenecks in computational complexity and memory requirements can be identified and addressed. Accordingly, a memory reduction scheme for the video segmentation unit, reducing bandwidth with more than 70%, and a low complexity morphology architecture that only requires memory proportional to the input image width, have been developed. On a system level, it is shown that a labeling unit based on a contour tracing technique does not require unique labels, resulting in more than 50% memory reduction. The hardware accelerators provide the tracking software with image objects properties, i.e. features, thereby decoupling the tracking algorithm from the image stream. A prototype of the embedded system is running in real-time, 25 fps, on a field programmable gate array development board. Furthermore, the system scalability for higher image resolution is evaluated.

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