Voltage step stress: a technique for reducing test time of device ageing

Abstract

Device ageing leads to circuit malfunction and must be controlled. During ageing, defects build up slowly and the test is time consuming and costly. The typical ageing tests are repeated ~5 times under different voltages. To reduce the test time, the voltage step stress (VSS) technique is proposed, which replaces the multiple tests under different voltage by a single test and saves time. This paper reviews the recent development of the VSS technique. After presenting its underlying principle, its applicability will be demonstrated for both the negative bias temperature instability and hot carrier ageing.