VPH: Versatile Routability-Driven Place Algorithm for Hierarchical FPGAs Based on VPR

Abstract

VPH (Versatile Placer for Hierarchical FPGAs, HFPGAs) is a place tool aiming at a routability-driven placement process for HFPGAs. It improves the placement algorithm of VPR (Versatile Place andRoute) by taking into consideration of specific constraints of hierarchical architectures for HFPGAs, and updates the place process based on it. Further more, thanks to the interconnect predictability, VPH can take into account routing constraints in early placement stage and evaluate efficiently the routability of the circuit.In this paper, we introduce the VPH design framework and its related placement algorithms. Its effectiveness is validated by the experimental results of MCNC benchmark.

Multilevel Optimization for Large-Scale Hierarchical FPGA Placement

“…Maidee [3] proposed a fast partition-based placement algorithm, together with a post-refinement step based on a lowtemperature simulated annealing process. There have some publications [4][5][6][7] concerning placement on FPGAs within Chinese academy circle. There are other papers focusing on FPGA CAD such as [8] published in Chinese top journal.…”