Vulnerability Analysis of Trivium FPGA Implementations

Potestad-Ordonez, F. E.; Jimenez-Fernandez, C. J.; Barrero, Manuel

doi:10.1109/tvlsi.2017.2751151

Cited by 16 publications

(32 citation statements)

References 29 publications

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“…In this case, if 'T-T Glitch ' is less than T min , it leads to an erroneous behavior. Figure 4 shows how a clock glitch can inject faults in the system and how these faults can propagate through the next clock cycles [17]. defined based on the system logic design and cannot be manipulated to perform fault injection.…”

Section: Clock Fault Injection Conceptmentioning

confidence: 99%

“…There are various practical techniques for generating a faulty clock signal [11,17,19,27,29,[37][38][39][40][41]48,49]. All of the proposed methods call for a high-frequency clock signal, the so-called 'Nominal Clock' on the clock fault generator side.…”

Section: A Review Of Previously Proposed Clock Glitch Generatorsmentioning

confidence: 99%

“…Today's simulation tools have extensive capabilities, and they can be used as highly accurate, flexible, and low-cost appliances in primary evaluation. However, in the domain of hardware-based attacks, since different environmental parameters are involved, it is not possible to describe and study any arbitrary attack in the simulation environment [17]. Moreover, using hardware simulators and accessing the processor hardware description is not feasible for the software developers.…”

Section: Introductionmentioning

confidence: 99%

“…Nevertheless, this technique cannot guarantee a high-quality assessment against hardware-based attacks that target post-implemented devices [14]. Technical considerations-including environmental effects, process variations, and subversive influences-still have a place [17]. The most considered technique for hardware security evaluation is based on experimental analysis that can provide a physical environment for investigating and measuring the consequences of possible risks [18][19][20].…”

Section: Introductionmentioning

confidence: 99%

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A Review on Evaluation and Configuration of Fault Injection Attack Instruments to Design Attack Resistant MCU-Based IoT Applications

et al. 2020

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The Internet-of-Things (IoT) has gained significant importance in all aspects of daily life, and there are many areas of application for it. Despite the rate of expansion and the development of infrastructure, such systems also bring new concerns and challenges. Security and privacy are at the top of the list and must be carefully considered by designers and manufacturers. Not only do the devices need to be protected against software and network-based attacks, but proper attention must also be paid to recently emerging hardware-based attacks. However, low-cost unit software developers are not always sufficiently aware of existing vulnerabilities due to these kinds of attacks. To tackle the issue, various platforms are proposed to enable rapid and easy evaluation against physical attacks. Fault attacks are the noticeable type of physical attacks, in which the normal and secure behavior of the targeted devices is liable to be jeopardized. Indeed, such attacks can cause serious malfunctions in the underlying applications. Various studies have been conducted in other research works related to the different aspects of fault injection. Two of the primary means of fault attacks are clock and voltage fault injection. These attacks can be performed with a moderate level of knowledge, utilizing low-cost facilities to target IoT systems. In this paper, we explore the main parameters of the clock and voltage fault generators. This can help hardware security specialists to develop an open-source platform and to evaluate their design against such attacks. The principal concepts of both methods are studied for this purpose. Thereafter, we conclude our paper with the need for such an evaluation platform in the design and production cycle of embedded systems and IoT devices.

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Section: Clock Fault Injection Conceptmentioning

confidence: 99%

Section: A Review Of Previously Proposed Clock Glitch Generatorsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Review on Evaluation and Configuration of Fault Injection Attack Instruments to Design Attack Resistant MCU-Based IoT Applications

et al. 2020

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“…In the case of the stream ciphers the number of works is even lower, being all of them presented using FPGAs implementations as [44] and as far as we know none of them applied to ASIC implementations. [3,4], [26][27][28], [30][31][32][33][34][35][36][37][38][39][40][41] [25], [29], [44][45][46] [ [42][43][44] In the case of the Trivium stream cipher the most important DFA analyses are the mentioned above [38][39][40][41]. These works are in Group A, and they base their analyses on ideal fault models or scenarios.…”

Section: Introductionmentioning

confidence: 99%

Breaking Trivium Stream Cipher Implemented in ASIC Using Experimental Attacks and DFA

Potestad-Ordonez

Barrero

Oliva

et al. 2020

Sensors

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One of the best methods to improve the security of cryptographic systems used to exchange sensitive information is to attack them to find their vulnerabilities and to strengthen them in subsequent designs. Trivium stream cipher is one of the lightweight ciphers designed for security applications in the Internet of things (IoT). In this paper, we present a complete setup to attack ASIC implementations of Trivium which allows recovering the secret keys using the active non-invasive technique attack of clock manipulation, combined with Differential Fault Analysis (DFA) cryptanalysis. The attack system is able to inject effective transient faults into the Trivium in a clock cycle and sample the faulty output. Then, the internal state of the Trivium is recovered using the DFA cryptanalysis through the comparison between the correct and the faulty outputs. Finally, a backward version of Trivium was also designed to go back and get the secret keys from the initial internal states. The key recovery has been verified with numerous simulations data attacks and used with the experimental data obtained from the Application Specific Integrated Circuit (ASIC) Trivium. The secret key of the Trivium were recovered experimentally in 100% of the attempts, considering a real scenario and minimum assumptions.

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Lightweight cryptographic algorithms based on different model architectures: A systematic review and futuristic applications

Bhagat¹,

Kumar²,

Gupta

et al. 2022

Concurrency and Computation

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Summary Lightweight cryptography is a rapidly developing research field. Its main goal is to provide security for devices with fewer resources. These limited‐resource devices implement reliable ciphers that use very little power and computation. The lightweight cipher should be built for high performance while using the fewest resources possible, such as memory and power. In this article, we compare block ciphers and several other stream ciphers based on criteria such as input size, output size, structure employed, key size, number of rounds, vulnerable attacks, chip area, gate equivalent, memory use, throughput, and security features. Moreover, this article provides a detailed analysis comparing all cryptographic algorithms and their use in day‐to‐day life activities. This paper also discusses some lightweight ciphers, stream ciphers, and hybrid ciphers. Moreover, it shows the cryptanalysis of some block ciphers like DES.

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Vulnerability Analysis of Trivium FPGA Implementations

Cited by 16 publications

References 29 publications

A Review on Evaluation and Configuration of Fault Injection Attack Instruments to Design Attack Resistant MCU-Based IoT Applications

A Review on Evaluation and Configuration of Fault Injection Attack Instruments to Design Attack Resistant MCU-Based IoT Applications

Breaking Trivium Stream Cipher Implemented in ASIC Using Experimental Attacks and DFA

Lightweight cryptographic algorithms based on different model architectures: A systematic review and futuristic applications

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