W‐band ×8 frequency multiplier in 65 nm CMOS with 25% bandwidth and 4.63 dBm output power

Abstract

This letter presents an ×8 frequency multiplier for the W‐band wireless satellite communication in the 65 nm complementary metal‐oxide‐semiconductor process. To reduce the power consumption, the proposed frequency multiplier employs only one driven amplifier and three stages of doublers. All doublers adopt balanced structures to increase their robustness. The output buffer is introduced to ameliorate the impedance matching of output port so that the output power of the proposed ×8 frequency multiplier can achieve 4.63 dBm. Through the special design of the interstage impedance matching circuit, the relative 3‐dB bandwidth of the proposed frequency multiplier is over 25% (from 74.8 to 96.2 GHz). The chip also has a small size and low power consumption, which is 1.37 × 0.51 mm2 and 125 mW, respectively.