W-CDMA 1 chip SiGe TX-IC with high dynamic range and accurate temperature compensation VGA

Ueda, Tetsuya; Ninomiya, Keiken; Takahashi, Yoshiaki; Matsunami, Yukitoshi; Joba, Hiroyuki; Itoh, Kenji; Malhi, T.S.; Wang, T.

doi:10.1109/rfic.2003.1213971

Cited by 2 publications

(1 citation statement)

References 4 publications

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“…The thermal and flicker contributions at the DAC output current noise can be expressed as follows: (4) where is the number of taps, is the transconductance of the rail device in the current source of Fig. 5(b), and contributions of the cascode device are neglected [25].…”

Section: A Rf Dac Linearitymentioning

confidence: 99%

A Linear $\Sigma$–$\Delta$ Digital IF to RF DAC Transmitter With Embedded Mixer

Taleie

Copani

Bakkaloglu

et al. 2008

IEEE Trans. Microwave Theory Techn.

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A noise-shaped direct digital IF to RF (DIF2RF) DAC with embedded upconverter mixer is presented. The digital IF signal is noise shaped by a bandpass 6-1 modulator with 1-bit IF output followed by a semidigital finite impulse response (FIR) filter. The current mode FIR filter combines scaled values of the local oscillator (LO) signal for performing reconstruction filtering and upconversion in a single module. The DIF2RF design modulates the digital IF signal with a digital LO signal. This topology eliminates the transconductance nonlinearity of conventional mixers and is inherently linear due to single-bit digital IF input. The presented architecture reduces clock jitter sensitivity of 1-bit DACs by masking IF clock transitions with LO signals. A prototype of the DIF2RF DAC is designed and fabricated in a five-layer metal 0.25-m digital CMOS process. The architecture can be used in low-power software-defined digital-IF transmitters. The DIF2RF DAC consumes 49 mA from a 2.5-V supply, achieving 64.7-dBc third-order intermodulation at 1.03 GHz with a spurious-free dynamic range of 72 dB in a 15-MHz bandwidth.

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Section: A Rf Dac Linearitymentioning

confidence: 99%