WCET Measurement-based and Extreme Value Theory Characterisation of CUDA Kernels

Abstract

Over the last few years, considerable interest has arisen in measurement-based probabilistic timing analysis. The term MBPTA has been used to indistinctly refer to a variety of different applications of Extreme Value Theory (EVT) to the timing analysis problem. The successful application of MBPTA techniques to a score of case studies has not fully dispelled the concerns that industrial stakeholders had with the quality of the computed bounds, hence ultimately with their industrial viability. Placing focus on the MBPTA methods and techniques developed in the PROARTIS and PROXIMA projects, collectively referred to as proMBPTA, we discuss the main misconceptions and pitfalls that can prevent a sound application of EVT-based WCET analysis. Using a combination of arguments and support examples, we show that proMBPTA is a rigorous process, fully amenable to sound and sustainable industrial use.

Probabilistic Worst-Case Timing Analysis

“…Individual approaches differ in the assumptions that they rest on and in the statistical tools that they use. At the outermost level, the research proposals divide between those that prescribe the use of randomization in the execution platforms [34,7] and those that assume unmodified (time-deterministic) platforms [21,53]. Experimental evidence shows that randomized execution platforms facilitate meeting the statistical prerequisites of EVT.…”

“…The same confidence levels are subsequently used to sustain the reliability of the results, in contrast with [34,7], which assess the quality of the pWCET distribution indirectly, as part of the parameter selection step. [21] uses EVT to analyze the timing behaviour of highly-parallel applications running on GPGPU. The MBPTA application procedure in the cited work broadly aligns with [34,26] except that the authors' interest is more centered on the assessment of the EVT statistical requirements, owing to the looser independence conditions of their problem.…”

A Perspective on Safety and Real-Time Issues for GPU Accelerated ADAS

“…Trivially, different vendors provide different implementations of all the blocks in Figure 1: more specifically, cache hierarchy, implementation details of the HW scheduling mechanisms, instruction decoding, branch prediction and ALU (Arithmetic Logic Units) pipelines might present significant differences. With respect to terminology, the processing cores in NVIDIA architectures are named Streaming Multiprocessors (SMs) 2 , whereas for recent ARM 3 designed integrated GPUs, as well as Intel integrated graphics devices, the term Execution Unit (EU) is used [1]; AMD uses the term (Next-Generation) Compute Unit (CU/NCU) 4 . Depending on how a GPU is connected to the rest of the system, a GPU can be implemented as an integrated device with respect to the CPU (iGPU) or as a discrete peripheral (dGPU).…”

Upper Bounds Prediction of the Execution Time of Programs Running on ARM Cortex-A Systems

“…Depending on the certain theoretical hypotheses of the EVT, the logical work flow of the framework derives its probabilistic pWCET estimate from traces of execution times. Concerning the DIAGnostic tool, K. Berezovskyi et al in [9], [10] also investigate different methods inside the EVT theory for Graphical Processor Units (GPUs). The main results showed that hardware time-randomization is not that essential for the applicability of EVT and can be applied even to some non-time-randomized systems as GPUs.…”