Wideband and scalable equivalent-circuit model for differential through silicon vias with measurement verification

Lu, Kuan-Chung; Horng, Tzyy‐Sheng

doi:10.1109/ectc.2013.6575725

Cited by 8 publications

(2 citation statements)

References 9 publications

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“…The parameters of the symbols in the model are listed in Table 2 . The values of each lumped element can be calculated by applying the dimensions [ 22 , 23 , 24 , 25 ] and material properties [ 26 , 27 , 28 ] in the following equations. The diameter, width, length, thickness, height, and spacing is symbolized d, w, l, t, h, and p, respectively.…”

Section: Structural Designmentioning

confidence: 99%

A RF Redundant TSV Interconnection for High Resistance Si Interposer

Wang

Jin

et al. 2021

Micromachines

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Through Silicon Via (TSV) technology is capable meeting effective, compact, high density, high integration, and high-performance requirements. In high-frequency applications, with the rapid development of 5G and millimeter-wave radar, the TSV interposer will become a competitive choice for radio frequency system-in-package (RF SIP) substrates. This paper presents a redundant TSV interconnect design for high resistivity Si interposers for millimeter-wave applications. To verify its feasibility, a set of test structures capable of working at millimeter waves are designed, which are composed of three pieces of CPW (coplanar waveguide) lines connected by single TSV, dual redundant TSV, and quad redundant TSV interconnects. First, HFSS software is used for modeling and simulation, then, a modified equivalent circuit model is established to analysis the effect of the redundant TSVs on the high-frequency transmission performance to solidify the HFSS based simulation. At the same time, a failure simulation was carried out and results prove that redundant TSV can still work normally at 44 GHz frequency when failure occurs. Using the developed TSV process, the sample is then fabricated and tested. Using L-2L de-embedding method to extract S-parameters of the TSV interconnection. The insertion loss of dual and quad redundant TSVs are 0.19 dB and 0.46 dB at 40 GHz, respectively.

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Section: Structural Designmentioning

confidence: 99%

A RF Redundant TSV Interconnection for High Resistance Si Interposer

Wang

Jin

et al. 2021

Micromachines

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“…In differential TSV transmission case, voltages on a pair of TSVs are compared and the difference is used to determine the output level. There are differential TSV models proposed in [14], [15], and [23]. These models analyze a pair of differential TSV with grounded TSV nearby.…”

Section: A Differential Tsv Impact On Modelingmentioning

confidence: 99%

Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling

Peng

Song

Petranovic

et al. 2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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This paper presents a silicon effect-aware multiTSV model. Through-silicon-via (TSV) depletion region, silicon substrate discharging path and electrical field distribution around TSV neighbor are modeled and studied in full-chip design. Verification with field solver and full-chip TSV-to-TSV coupling analysis in both the worst case and the average case show this model is accurate and efficient. It is found that 3-D nets receive more noise than their 2-D counterparts due to TSV-to-TSV coupling. To alleviate this coupling noise on TSV nets, two new optimization methods are investigated. One way is to utilize guard rings around the victim TSV so as to form a stronger discharging path, an alternative approach is to adopt differential signal transmission to improve noise immunity. These techniques have been implemented on 3-D IC designs with TSVs placed regularly or irregularly. Full-chip analysis results show that our approaches are effective in noise reduction with small area overhead.

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Effect of substrate contacts on reducing crosstalk noise between TSVs

Watanabe

Karel

Niioka

et al. 2014

2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

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We propose a model for coupling that considers substrate contacts between through silicon vias (TSVs) in bulk-CMOS technologies. The proposed model is compact but has reasonable accuracy for the dense substrate contacts in largescale three dimensional integrated circuits (3D ICs). We describe the modeling for substrate contacts with the equivalent electrical circuit, discuss the impact of substrate contacts on the electrical parasitic parameters, and clarify the effect of substrate contacts on reducing crosstalk noise and increasing delay. Results of analysis show that if substrate contacts are not considered, crosstalk noise becomes the overestimate of 5 to 700 times and delay becomes the underestimate of 1.4 to 2.4 times.

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Wideband and scalable equivalent-circuit model for differential through silicon vias with measurement verification

Cited by 8 publications

References 9 publications

A RF Redundant TSV Interconnection for High Resistance Si Interposer

A RF Redundant TSV Interconnection for High Resistance Si Interposer

Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling

Effect of substrate contacts on reducing crosstalk noise between TSVs

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