Work-in-Progress: A Flexible Router Architecture for 3D NoCs

Khamis, Mostafa; Said, Mostafa; Shalaby, Ahmed

doi:10.1109/rtss.2017.00044

Cited by 2 publications

(1 citation statement)

References 5 publications

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“…This router was also verified and tested using the environment in [11] [12]. The 3D networks routers [13] could be studied and implemented in future work.…”

Section: B Configurable Routermentioning

confidence: 99%

RVNoC: A Framework for Generating RISC-V NoC-Based MPSoC

Elmohr

Eissa

Ibrahim

et al. 2018

2018 26th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)

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With the increase in the number of cores embedded on a chip; The main challenge for Multiprocessor Systemon-Chip (MPSoC) platforms is the interconnection between that massive number of cores. Networks-on-Chip (NoC) was introduced to solve that challenge, by providing a scalable and modular solution for communication between the cores. In this paper, we introduce a configurable MPSoC framework called RVNoC that generates synthesizable RTL that can be used in both ASIC and FPGA implementations. The proposed framework is based on the open source RISC-V Instruction Set Architecture (ISA) and an open source configurable flit-based router for interconnection between cores, with a core network interface of our design to connect each core with its designated router. A benchmarking environment is developed to evaluate variant parameters of the generated MPSoC. Synthesis of a single building block containing a single core without any peripherals, a router, and a core network interface, using 45nm technology, shows an area of 102.34 kilo Gate Equivalents (kGE), a maximum frequency of 250 MHz, and a 9.9 μW/MHz power consumption.

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“…This router was also verified and tested using the environment in [11] [12]. The 3D networks routers [13] could be studied and implemented in future work.…”

Section: B Configurable Routermentioning

confidence: 99%