X-Ray Metrology for the Semiconductor Industry

Abstract

The scaling of traditional CMOS processes, and their associated metrologies, to produce smaller and faster devices was very successful down to the 90 nm node. However, to progress further, it has been found necessary to use novel materials, for which established metrologies are inadequate. In this article we demonstrate with examples that X-Ray Metrology (XRM) methods are particularly well-suited to provide characterization and measurement of the new materials systems being considered for advanced silicon processing, and for meeting the requirements of sub-90 nm nodes. These methods can be used for materials research, process development and integration and for in-line process control of product wafers.It has been clear for some time that lithography scaling alone will not meet Moore's Law projections in manufacturing at the 90 nm node and below. New materials, processes and manufacturing technologies are required to achieve the required improvements in device performance. As a result, various scaling strategies at the front end, other than lithography, are now being explored. These are illustrated in Figure 1 and include improved quality as well as scale of lithography, carrier mobility engineering through strained silicon and increased gate stack capacitance through use of high-κ dielectrics and metal gates. Even at the 65 nm node, the integration of at least one of these technologies is essential to achieve the desired level of performance in high-end logic devices, and many more new materials are being introduced at the 45 nm node. New high-κ materials are also required to reduce cell size for DRAM manufacturers. Exotic materials such as multi-layer nanolaminates are being explored to meet the need for a capacitor dielectric with both high-κ and a suitable band gap. Furthermore, a technology shrink is also required for back-end processing. For example, for the 65 nm nodes, a traditional PVD (plasma vapor deposition) barrier metal process would represent 40% of an overall copper interconnect, thus impacting overall resistivity. New barrier materials are being explored in order to maintain RC delays within ITRS i guidelines.It is a significant challenge simply to measure such extremely thin layers of these new materials. For example, their optical constants in very thin layers are normally not known and assuming bulk values is likely to give rise to large errors. Furthermore, monitoring thickness alone may not be sufficient, especially in cases where the microstructure of the layers is significant. The leakage current of high-κ dielectrics and the work functions of metal gates are affected by their crystalline/amorphous ratios. Information on the microstructure of deposited materials is now key to determining their electronic properties. This has never been required previously in semiconductor manufacturing i ITRS = International Technology Roadmap for Semiconductors