XY Based Fault-Tolerant Routing with the Passage of Faulty Nodes

Kurokawa, Yota; Fukushi, Masaru

doi:10.1109/candarw.2018.00027

Cited by 6 publications

(1 citation statement)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In faultfree situations, it serves as a traditional XY routing algorithm, but it switches from XY to YX routing in the event of failure. Further in [15], the authors added extra switches and links to the router architecture. Switches at the failed node transfer the data to spare links.…”

Section: Related Workmentioning

confidence: 99%

Reinforcement Learning Based Fault-Tolerant Routing Algorithm for Mesh Based NoC and Its FPGA Implementation

et al. 2022

View full text Add to dashboard Cite

Network-on-Chip (NoC) has emerged as the most promising on-chip interconnection framework in Multi-Processor System-on-Chips (MPSoCs) due to its efficiency and scalability. In the deep sub-micron level, NoCs are vulnerable to faults, which leads to the failure of network components such as links and routers. Failures in NoC components diminish system efficiency and reliability. This paper proposes a Reinforcement Learning based Fault-Tolerant Routing (RL-FTR) algorithm to tackle the routing issues caused by link and router faults in the mesh-based NoC architecture. The efficiency of the proposed RL-FTR algorithm is examined using System-C based cycle-accurate NoC simulator. Simulations are carried out by increasing the number of links and router faults in various sizes of mesh. Followed by simulations, real-time functioning of the proposed RL-FTR algorithm is observed using the FPGA implementation. Results of the simulation and hardware shows that the proposed RL-FTR algorithm provides an optimal routing path from the source router to the destination router.

show abstract

Section: Related Workmentioning

confidence: 99%