22nd IEEE VLSI Test Symposium, 2004. Proceedings.
DOI: 10.1109/vtest.2004.1299232
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Yield analysis of logic circuits

D. Appello
1
,
A. Fudoli
2
,
K. Giarda
3
et al.
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Cited by 13 publications
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References 12 publications
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Yield enhancement through fast statistical scan test analysis for digital logic

Erb
1
,
Burmer
2
,
Leininger
3
IEEE/SEMI Conference and Workshop on Advanced Semiconductor Manufacturing 2005.
6
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Yield enhancement through fast statistical scan test analysis for digital logic

Erb
1
,
Burmer
2
,
Leininger
3
IEEE/SEMI Conference and Workshop on Advanced Semiconductor Manufacturing 2005.
6
0
0
0
View full textAdd to dashboardCite

Application of Bayesian Machine Learning To Create A Low-Cost Silicon Failure Mechanism Pareto

Schuermyer
1
,
Palosh
2
,
Babighian
3
et al. 2019
2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)
3
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Improving Performance of Effect-Cause Diagnosis with Minimal Memory Overhead

Tang
1
,
Liu
2
,
Cheng
3
et al. 2007
16th Asian Test Symposium (ATS 2007)
9
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