1993
DOI: 10.1109/4.222176
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Yield optimization of analog ICs using two-step analytic modeling methods

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Cited by 15 publications
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“…The CPU time can be reduced with the response surface method [136], which works in two steps. First, the parameter space is sampled with controlled simulations according to some design-of-experiments (DOE) scheme.…”
Section: E Yield Estimation and Optimizationmentioning
confidence: 99%
“…The CPU time can be reduced with the response surface method [136], which works in two steps. First, the parameter space is sampled with controlled simulations according to some design-of-experiments (DOE) scheme.…”
Section: E Yield Estimation and Optimizationmentioning
confidence: 99%