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The stresses occurring in the solder joints during thermal loads have been studied by finite element analysis. Besides the cases of no underfill and perfect adhesion, underfill delaminations at the interfaces to the solder, to the chip, and to the substrate surfaces, respectively, have been considered. The simulation results indicate that rapid failing of the flip-chip modules due to delamination can be prevented effectively by using an underfill that has a high Young’s modulus at room temperature (even 20 GPa are not too high) and a CTE slightly lower than solder. Since the ultimate failure is always caused by growing of a major crack, the damage integral concept is valid for lifetime estimations even in the case of FC modules with underfill.

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Stress-voiding and electromigration have become urgent reliability concerns at the decrease of interconnect dimensions to submicron size. Severe stress voiding may arise in multilevel metallizations, particularly at contact and via regimes where the thermal stresses are highest. Via and contact structures with the attached refractory layers usually block entirely the electromigration flux; hence, EM voids are likely to form here. In this paper we first model the migration of atoms due to gradients in composition, stress, and electric potential. We seek a formulation in the spirit of irreversible thermodynamics, i.e. without reference to any specific micromechanisms of diffusion. We then apply the general developments to predict the stress evolution and void growth in Al based interconnect lines confined between entirely blocking Wstuds. We also analyze the effects of Cu depletion at vias, either by interfacial or grain boundary diffusion, on the stress evolution and void growth. Finally we demonstrate that the change in the line resistance due to void growth will display apparent incubation times even if the void grows linearly with time.

No abstract