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For the first time, embedded Si:C (eSi:C) was demonstrated to be a superior nMOSFET stressor compared to SMT or tensile liner (TL) stressors. eSi:C nMOSFET showed higher channel mobility and drive current over our best poly-gate 45nm-node nMOSFET with SMT and tensile liner stressors. In addition, eSi:C showed better scalability than SMT plus tensile liner stressors from 380nm to 190nm poly-pitches.

Band-gap engineering using SiGe channels to reduce the threshold voltage (V TH ) in p-channel MOSFETs has enabled a simplified gate-first high-κ/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafers for SOC applications has unique challenges like the oxidation rate differential with silicon, defectivity and interface state density in the unoptimized state, and concerns with T inv scalability. In overcoming these challenges, we show that we can leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) HKMG CMOS logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.Introduction:

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