I. AbstractIn this paper we show a Depleted-Substrate Transistor (DST) technology which demonstrates significant performance gain over bulk Si transistors without the floating body effect (FBE). We have fabricated depleted-substrate CMOS transistors on thin silicon body (130nm) with physical gate lengths down to 50nm which show much steeper subthreshold slopes (<75mV/decade) and improved DIBL (15OmVN) over both partially-depleted (P-D) SO1 and bulk Si, for both PMOS and NMOS transistors. The salicide formation and high parasitic resistance problems associated with the use of thin Si body can be overcome by using raised source/drain. Depleted-substrate PMOS transistors with 50nm physical gate length and raised source/drain were fabricated and achieved I,,,, = 0.65mA/um and I,,@ = 9nNum at V, = 1.3V. This PMOS drive current is the highest ever reported, and is about 30% higher than any previously published PMOS I,,, value for both PD-SO1 and bulk Si at a given bff. The use of raised source/drain improved the I,,,, of the depleted-substrate NMOS transistors by -20%. Depletedsubstrate NMOS transistors with 65nm physical gate length and raised source/drain achieved DIBL = 45mVN, subthreshold slope = 75mV/decade, I,,,, = 1.18mAlum and I,,@ = 60nA/um at V,, = 1.3V, as well as significant improvement in Id-Vd characteristics due to a 60% reduction in DIBL and >25% improvement in subthreshold slope over the bulk Si.
II. IntroductionThere are two kinds of planar SO1 transistor structures, namely the partially-depleted (P-D) SO1 and fully-depleted (F-D) SOI. Previously we evaluated P-D SO1 CMOS transistors and concluded that P-D SO1 has diminishing performance gain with scaling over standard bulk Si CMOS [l, 21. In addition, standard P-D SO1 transistors exhibit FBE which puts a significant burden on circuit design. On the other hand, it is well-known that fully-depleted (F-D) SO1 transistors eliminate the FBE while providing better subthreshold slopes than bulk Si transistors [3-51. However, there are very few reports on F-D SO1 transistors with physical gate lengths less than 100nm, and the scalability of F-D SO1 technology is unknown. In this paper we evaluate a thin-silicon-body depleted-substrate transistor technology with a focus on sub-70nm physical gate lengths and examine its scalability and performance down to 50nm. We give this transistor technology a generic name of Depleted-Substrate -Transistor (DST).
III. ProcessSub-70nm depleted-substrate CMOS transistors were fabricated on thin silicon body with thickness 530nm on top of a -200nm buried oxide. The physical gate oxide thickness was equal to 1 Snm. Figure 1 shows a TEM cross section of a thin-silicon-body depleted-substrate transistor. To overcome the salicide formation and high parasitic resistance problems in thin-silicon-body devices, raised source/drain can be used. Figure 2 shows a TEM cross section of the DST with raised source/drain. In this experiment depleted-substrate transistors with and without raised source/drain were fabricated down to 50nm. Stan...
