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In this work, HCI effect of PMOS FETs was studied. For a given drain bias, electron trapping is the dominant degradation mechanism for a gate bias close to 20% of the drain bias. A maximum gate current is seen under this bias condition. Hole trapping is dominant when the gate bias is equal to the drain bias where drain current is the maximum. Electron trapping enhances PMOS driving current or Idsat whereas hole trapping degrades Idsat. The effect of electron trapping and hole trapping cancel each other. As a result, life time is longer when two trapping mechanisms are involved compared with the life time with one trapping mechanism. In this study, device Idsat degradation was measured with different gate and drain biases in a DC mode. An AC stress is also performed in which gate/drain bias waveforms follow those of a typical switching inverter. Due to the above mentioned cancelling effect, PMOS HCI AC life time is longer and the DC to AC conversion factor is much larger than conventionally used values. The effect of STI stress on HCI degradation is briefly studied. Layouts to minimize this effect are then proposed.

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