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We present a new collector construction for high-speed SiGe:C HBTs that substantially reduces the parasitic base-collector capacitance by selectively underetching of the collector region. The impact of the collector module on RF performance is demonstrated in separate bipolar processes for npn and pnp devices. A minimum gate delay of 3.2ps was achieved for CML ring oscillators with npn transistors featuring fT/ f , , values of 300GHd250GHz at BVCEo = 1 AV. For pnp devices with fT/ f, , , values of 135GHz I140GHr at BVCEO = 2.W a gate delay of 5 . 9~~ is demonstrated. Further vertical scaling of the doping profiles increases fT to 380GHz at BVcEo = 1.5V for npn's and 155GHz at BVcEo = 2.3V for pnp's, but ring oscillator speed and fmax degraded.

We demonstrate a BiCMOS process which uses only 22 mask steps to fabricate four types of SiGe:C HBTs, in combination with a triple-well, 2.5V CMOS core and a full menu of passive elements. Key process feature is a 2-mask HBT module. We show that transistors with peak fT values ranging from 3OGHz (@ 7V BV, , ) up to 130GHz (@ 2.1V BVczo) can he fabricated with this low-cost module. Among the passives are varactors, polysilicon resistors, and a 2fF/pmz MIMsapacitor. Five layers of AI are available, including 2pm and 3pm thick upper layers. SOC ability of the process is demonstrated by a 1M-SRAM yield of typically 70%.

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