The radiation is, for the most part, generated by common-mode currents. This paper shows that action on layout can reduce common-mode currents effectively. Cost-effective, the common-mode current control enables the radiation level knowledge at the conception of a device. This is an important gain of time. Four Boost structures are studied in order to validate first, experimentally and second by modelling, reduction common-mode current layouts, supposed effective. The simulated models are based on the partial equivalent element circuit (PEEC) method. We show also the impact of these layout techniques on radiated perturbations.

No abstract

Inverters used in adjustable speed drives create common mode voltages with high dvldt transitions resulting in high frequency common mode currents which flow to the ground through stray capacitances. These common mode currents are known to damage the bearings of electric machines and cause malfunctions in other surrounding electronic devices, and therefore need to be confined by using bulky and expensive electromagnetic compatibility (EMC) filters. The presented work focuses on the three levels neutral-point-clamped (NPC) inverter and proposes a new pulse width modulation (PWM) strategy for the reduction of common mode currents by lowering the number of step variations of the common mode voltage. Unlike previous strategies, this carrier-based PWM pays attention to the real phenomena involved in the generation of common mode currents so as to efficiently reduce them by avoiding dead time effects. The new strategy has been implemented in a 20 kVA prototype and the experimental results presented in this paper confirm its best EMC behavior compared with classical PWM.

No abstract

No abstract