Silicon is the predominant semiconductor in photovoltaics. However, the conversion efficiency of silicon single junction solar cells is intrinsically constrained to 29.4%, and practically limited around 27%. It is nonetheless possible to overcome this limit by combining silicon with high bandgap materials, such as III-V semiconductors, in a multi-junction device. Despite numerous studies tackling III-V/Si integration, the significant challenges associated with this material combination has hindered the development of highly efficient III-V/Si solar cells. Here we demonstrate for the first time a III-V/Si cell reaching similar performances than standard III-V/Ge triple-junctions solar cells. This device is fabricated using wafer bonding to permanently join a GaInP/GaAs top cell with a silicon bottom cell.The key issues of III-V/Si interface recombination and silicon weak absorption are addressed using polysilicon/SiOx passivating contacts and a novel rear side diffraction grating for the silicon bottom cell. With these combined features, we demonstrate a 2-terminal GaInP/GaAs//Si solar cell reaching a 1sun AM1.5g conversion efficiency of 33.3%.

Reducing the temperature needed for high strength bonding which was and is driven by the need to reduce effects of coefficient of thermal expansion mismatch, reduce thermal budgets, and increase throughput has led to the development of plasma treatment procedures capable of bonding Si wafers below 300 °C with a bond strength equivalent to Si bulk. Despite being widely used, the physical and chemical mechanisms enabling low temperature wafer bonding have remained poorly understood. We developed an understanding of the beneficial surface modifications by plasma and a model based on short range low temperature diffusion through bonding experiments combined with results from spectroscopic ellipsometry, depth resolving Auger electron spectroscopy, and transmission electron microscopy measurements. We also present experimental results showing that even at room temperature reasonable bond strength can be achieved. We conclude that the gap closing mechanism is therefore a process which balances the lowering of the total energy by minimizing the sum of the free surface energy (maximizing the contact area between the surfaces) and strain energy in the oxide at the bond interface.

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Myriad structures for stacking chips, power devices, smart cards, and thin substrates for processors have one thing in common: thin silicon. Wafer thinning will soon be an essential process step for most of the devices fabricated and packaged henceforth. The key driving forces for thinned wafers are improved heat dissipation, three-dimensional stacking, reduced electrical resistance, and substrate flexibility. Handling of thin and ultrathin substrates however is not trivial because of their fragility and tendency to warp and fold. The thinned substrates need to be supported during the backside grinding process and through the subsequent processes such as lithography, deposition, etc. Using temporary adhesives to attach the processed device wafer to a rigid carrier wafer offers an efficient solution. The key requirements for such materials are ease of application, coating uniformity with minimal thickness variation across the wafer, good adhesion to a wide variety of surfaces, thermal stability in processes such as dielectric deposition and metallization, and ease of removal to allow high throughput. An additional requirement for these materials is stability in harsh chemical environments posed by processes such as etching and electroplating. Currently available materials meet only a subset of these requirements. None of them meet the requirement of high-temperature stability combined with ease of removal. We have developed adhesives that meet a wide range of post-thinning operating temperatures. Additionally, the materials are soluble in industry-accepted safe solvents and can be spin-applied to required thicknesses and uniformity. Above all, the coatings can be removed easily without leaving any residue. This paper reports on the development of a wide range of temporary adhesives that can be used in wafer thinning applications while applying both novel and conventional bonding and debonding methods.

A novel wafer bonding technology, designed to enable covalent and conductive wafer bonding processes at low temperature was developed. Covalent and conductive bonding processes at low temperatures and even room temperature may become key technology in order to fabricate high performance junctions in compound semiconductor integration applications.This work is presenting the first process qualification results obtained for Si wafers. Apart from equipment characterization data, e.g. particle contamination, data presented here include HR-TEM, EDXS and bond strength analysis achieved for Si-Si hydrophobic wafer bonding.