It is difficult for structural over-complete dictionaries such as the Gabor function and discriminative over-complete dictionary, which are learned offline and classified manually, to represent natural images with the goal of ideal sparseness and to enhance the difference between background clutter and target signals. This paper proposes an infrared dim target detection approach based on sparse representation on a discriminative over-complete dictionary. An adaptive morphological over-complete dictionary is trained and constructed online according to the content of infrared image by K-singular value decomposition (K-SVD) algorithm. Then the adaptive morphological over-complete dictionary is divided automatically into a target over-complete dictionary describing target signals, and a background over-complete dictionary embedding background by the criteria that the atoms in the target over-complete dictionary could be decomposed more sparsely based on a Gaussian over-complete dictionary than the one in the background over-complete dictionary. This discriminative over-complete dictionary can not only capture significant features of background clutter and dim targets better than a structural over-complete dictionary, but also strengthens the sparse feature difference between background and target more efficiently than a discriminative over-complete dictionary learned offline and classified manually. The target and background clutter can be sparsely decomposed over their corresponding over-complete dictionaries, yet couldn't be sparsely decomposed based on their opposite over-complete dictionary, so their residuals after reconstruction by the prescribed number of target and background atoms differ very visibly. Some experiments are included and the results show that this proposed approach could not only improve the sparsity more efficiently, but also enhance the performance of small target detection more effectively.

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A 2.5 GS/s 14-bit D/A converter (DAC) with 8 to 1 MUX is presented. This 14-bit DAC uses a “5+9” segment PMOS current-steering architecture. A bias circuit which ensures the PMOS current source obtains a larger output impedance under every PVT (process, source voltage and temperature) corner is also presented. The 8 to 1 MUX has a 3 stage structure, and a proper timing sequence is designed to ensure reliable data synthesis. A DEM function which is merged with a “5-31” decoder is used to improve the DAC's dynamic performance. This DAC is embedded in a 2.5 GHz direct digital frequency synthesizer (DDS) chip, and is implemented in a 0.18 μm CMOS technology, occupies 4.86 × 2. 28 mm2 including bond pads (DAC only), and the measured performance is SFDR > 40 dB (with and without DEM) for output signal frequency up to 1 GHz. Compared with other present published DACs with a non-analog-resample structure (means return-to-zero or quad-switch structure is unutilized), this paper DAC's clock frequency (2.5 GHz) and higher output frequency SFDR (> 40 dB, up to 1 GHz) has some competition.

A 2.5 GHz Direct Digital Frequency Synthesizer (DDS) with spurious noise cancellation is presented. Seven auxiliary DDSs have been used as spur cancellers which can generate opposition signal to counteract the spurs in DDS's output spectrum. Principle of spur cancellation and its implementation scheme is discussed. Key steps of spur cancellation procedure are also described. This DDS is implemented in a 0.18 µm CMOS technology, occupies 4.6 mm # 4.2 mm including bond pads. Measured performance is SFDR > 58 dB for output signal frequencies up to 1 GHz, more than 20 dB's improvement is achieved comparing to its intrinsic SFDR performance.

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