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A newly developed DNA measurement method for multiple single nucleotide polymorphism (SNP) typing using a radio-frequency identification (RFID) sensor chip was demonstrated. The RFID sensor chip monolithically integrates a sensor, amplifier, analog-to-digital converter (ADC), and a passive wireless communication interface for receiving commands and transmitting data on a 2.5×2.5 mm2 silicon chip. For the simultaneous multitarget measurement, anticollision control and peak-power suppression are essential. To assign a unique identification number (UID) for the identification of multiple sensor chips, a reproducible random number generator circuit (RRG) was designed and installed on the chip. Peak-power consumption was reduced to 1018 µW by a clock gating of functional circuit blocks. Multiple SNP typing was carried out by simultaneously operating five RFID sensor chips (four with photosensors and one with a temperature sensor). The target DNA was captured on the sensor chips, and SNPs were detected by observing bioluminescence. Finally, the observed data were wirelessly transmitted to the reader.

For the people involved with multi-Gb/s chip-to-chip serial links, reducing power dissipation per Gb/s to less than 1mW/(Gb/s) (i.e., 1pJ/b) has been a long-held goal. Several years ago, the power dissipation of these links was in the range of about 10 to 20mW/(Gb/s). In 2007, Poulton et al. developed a 14mW 6.25Gb/s transceiver with power efficiency of 2.2mW/(Gb/s) [1]. Thereafter, there were some efforts aiming to reduce power of each building block in a transceiver [2,3]. This paper presents a 12.3mW 12.5Gb/s complete transceiver (including CDR, MUX/DEMUX, and global clock distribution)in 65nm CMOS with power efficiency of 0.98mW/(Gb/s). To achieve low power, a resonant-clock distribution with distributed on-chip inductors and a low-swing voltage-mode driver with pulse-current boosting are used in the transmitter, while a symbol-rate comparator/phase detector using 4-stage sense amplifier and phase-rotating PLL with variable delay are used in the receiver. Figure 20.5.1 shows the block diagram of the transmitter (TX). The upper figureshows the output driver circuit. The output stage consists of a low-swing voltage-mode driver and a pulse-current driving circuit for improving rise/fall time (Tr/Tf). The voltage-mode driver is powered by two local voltage sources, VOH (about 0.7V) and VOL (about 0.3V), which are generated by on-chip regulators from a 1.0V supply. It is divided into three binary-weighted slices. The output impedance can be adjusted to 50Ω by trimming the number of "on" slices. On the other hand, the pulse-current driving circuit, directly powered by a 1.0V supply, shortens Tr/Tf by injecting pulse current into the output nodes at data transitions. Logical operations between the data signal itself and the delayed data signal generate pulse signals that drive the pulse-current driving circuit. The duration of pulse current can be changed by varying the delay time of the delayed data. Adequate "pre-emphasis" effect can therefore be obtained by adjusting the variable delays according to the loss of the transmission channel. Note that the output-voltage shifts at the data transition are performed mostly by the pulse-current driver, while the voltage-mode driver only takes charge of maintaining the output voltage as long as the data is consecutive and identical.The lower half of Fig. 20.5.1 outlines the 6.25GHz global-clock-distribution network. 6 horizontally located transmitters (and one dummy channel), each have a width of 400µm, share one on-chip PLL. To deliver a 6.25GHz clock to each TX, a resonant clock-distribution network that resonates a total of 8 spiral inductors (12 turns, L=12nH, and Q=6.2) located in each TX and wiring capacitance (0.3pF/mm), is used. Electromagnetic simulations show that this resonant networks has an impedance peak of 360Ω (Q=2.5) at 6.25GHz.Figure 20.5.2 shows a block diagram of the receiver (RX). The AC-coupled RX input is fed into a common-gate variable-gain amplifier (VGA). By varying the resistances of its termination resistors, the gain of the VGA can be switched ...