We experimentally demonstrate high-speed visible light communication (VLC) and high-quality solid-state lighting (SSL) using polymethyl-methacrylate-doped phosphor film based on cesium lead bromide quantum dot ( CsPbB r 3 -QD) and potassium fluorosilicate K 2 Si F 6 : M n 4 + , which is excited by a blue gallium nitride laser diode. A 1.6 Gbps data rate is achieved by employing a non-return-to-zero on–off keying modulation scheme. The measured bit error rate of 2.7 × 10 − 3 adheres to the standard threshold ( 3.8 × 10 − 3 ) of forward error correction. Moreover, the generated white-light source has a high color rendering index of 93.8 and a correlated color temperature of 4435 K, and it exhibits a Commission Internationale de l’Eclairage (CIE) 1931 chromaticity coordinate at (0.3556, 0.3520), which is close to the ideal CIE value of white light (0.3333, 0.3333). This work opens up exciting possibilities for future high-speed indoor VLC and high-quality SSL.

A high performance RFCMOS SoC GPS navigation solution is introduced. It supports various location and navigation applications, including autonomous GPS, SBAS, DGPS (RTCM), and AGPS in L1-band at 1575.42MHz. A wide range of reference frequencies are supported to comply with other handheld specifications. The base-band architecture is optimized for the correlation efficiency and the power consumption of one single correlating operation. Hence this SoC receiver achieves the industry's highest levels of sensitivity, accuracy, and Time-to-First-Fix (TTFF) with the lowest power consumption. PMIC is also integrated in the SoC, no external LDO and power switching circuit is needed for all voltage domains, including RTC.As mobile devices with GPS/navigation feature and location-based-service (LBS) become more and more popular, single chip GPS SoC receiver becomes the main trend [1][2][3]. A low power SiGe BiCMOS GPS radio for cell phones is introduced in [4]. This chip achieves low power, high performance and is highly integration with minimum external components compared to [1][2][3][4]. The block diagram is shown in Fig. 14.3.1. The RF frond-end, GPS engine, PMIC, ARM processor and peripheral controllers are all integrated in a single SoC.For the RF part, this chip delivers a total receiver noise figure of 3.2 dB with integrated LNA. With on-chip image-rejection mixer, the specification of an external SAW filter is alleviated, and with embeded automatic center frequency calibration band pass filter, an external filter is not required. To achieve the RF performance with CMOS SoC, Native NTN is put between RF and digital baseband to create a high resistance substrate. For RF sensitive blocks, P+ guard ring is used, and for RF noisy blocks, D-NWELL guard ring is chosen. The floorplan is also considered and RF macro is put at the upper left corner to minimize the noise from two sides only. Low frequency RTC and memories are put beside the RF part as an isolation component. Ground balls for RF are independent, and sensitive RF pins are surrounded by the ground for separation. In order to minimize the interference to RF in-band, the harmonics of PLL output frequencies are analyzed to make sure no high-order harmonics may drop in the range. A wide range of reference frequencies can be supported, and a low-power integer-N mode is provided for some commonly used frequencies, such as 16.368 and 26MHz. Up to 25% of RF current consumption can be saved with integer-N mode.Various power schemes are supported with internal PMIC integration. No external LDOs are needed and a single power supply ranging from 3.3 to 4.2V is enough for all power requirements. A low quiescent-current LDO is integrated in RTC domain. It is also the first GPS SoC that integrates a switching mode power supply (SMPS) to support energy-lossless voltage transfer. Its interference to RF part is suppressed by carefully controlling the voltage/current slew rate and the size of power MOS pre-driving circuit. The leakage current of the whole RTC domain, including LDO...

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