This paper presents a reconfigurable radio frequency to direct current (RF-DC) converter operating at 902 MHz frequency designed to efficiently harvest RF signals and convert into useable DC voltages for RF energy harvesting applications. The proposed scheme employs a dual-path, a series (lowpower) path and a parallel (high-power) path, to maintain high power conversion efficiency (PCE) over wide input power range. The dual-path is composed of two identical rectifier blocks utilizing internal threshold voltage cancellation (IVC) technique to efficiently compensate the threshold voltage of the transistors used as rectifying devices. An adaptive control circuit (ACC) consisting of a comparator, an inverter and three switches is used in the proposed scheme. The ACC activates the series path or the parallel path to maximize the harvested power based on the input power range. The proposed scheme is designed and fabricated in a 180 nm complementary metal-oxide semiconductor (CMOS) technology. The measurement results show that PCE of the proposed circuit is above 20% from −18 dBm to −5 dBm, maintaining 13-dB input power range with peak PCE of 33% at −8 dBm for 200 k load resistance. The proposed circuit demonstrates −20.2 dBm sensitivity across 1 M load resistance while producing 1 V output DC voltage. INDEX TERMS CMOS technology, dual path, power conversion efficiency, reconfigurable, RF-DC power converter, RF energy harvesting.

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Abstract:In this paper, a low-power reconfigurable ambient Radio Frequency to Direct Current power (RF-DC) converter using an internal threshold voltage cancellation (IVC) scheme with an auxiliary transistors block is presented. A maximum power point tracking (MPPT) algorithm is implemented in order to maintain the high efficiency by automatically selecting the number of stages. The proposed reconfigurable converter efficiently converts the RF signals to DC voltage by dynamically controlling the threshold voltage of the forward and reversed-biased transistors in the primary rectification body. During positive half-cycle, the proposed RF-DC converter reduces the voltage drop across the forward-biased transistors, which results in increased harvested power and output DC voltage. During negative half cycle, the proposed rectifier minimizes the reverse leakage current and prevents the loss of energy stored in the prior stages. A five-stage internal threshold compensated power converter is designed in 0.18 µm Complementary Metal-Oxide-Semiconductor (CMOS) technology with an active die area of 360 µm × 160 µm, while the Maximum Power Point Tracking (MPPT) occupies an active die area of 730 µm × 280 µm. The proposed scheme obtains maximum post-simulated power conversion efficiency (PCE) of 39.3% when input power level is −15 dBm and produces an output voltage of 3.3 V for a load of 1 MΩ and at a frequency of 900 MHz. The proposed scheme achieves a voltage sensitivity of 1V at a remarkably low input power of −21 dBm for a 1 MΩ load.

This paper presents a low power Gaussian Frequency-Shift Keying (GFSK) transceiver (TRX) with high efficiency power management unit and integrated Single-Pole Double-Throw switch for Bluetooth low energy application. Receiver (RX) is implemented with the RF front-end with an inductor-less low-noise transconductance amplifier and 25% duty-cycle current-driven passive mixers, and low-IF baseband analog with a complex Band Pass Filter(BPF). A transmitter (TX) employs an analog phase-locked loop (PLL) with one-point GFSK modulation and class-D digital Power Amplifier (PA) to reduce current consumption. In the analog PLL, low power Voltage Controlled Oscillator (VCO) is designed and the automatic bandwidth calibration is proposed to optimize bandwidth, settling time, and phase noise by adjusting the charge pump current, VCO gain, and resistor and capacitor values of the loop filter. The Analog Digital Converter (ADC) adopts straightforward architecture to reduce current consumption. The DC-DC buck converter operates by automatically selecting an optimum mode among triple modes, Pulse Width Modulation (PWM), Pulse Frequency Modulation (PFM), and retention, depending on load current. The TRX is implemented using 1P6M 55-nm Complementary Metal–Oxide–Semiconductor (CMOS) technology and the die area is 1.79 mm2. TRX consumes 5 mW on RX and 6 mW on the TX when PA is 0-dBm. Measured sensitivity of RX is −95 dBm at 2.44 GHz. Efficiency of the DC-DC buck converter is over 89% when the load current is higher than 2.5 mA in the PWM mode. Quiescent current consumption is 400 nA from a supply voltage of 3 V in the retention mode.

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