0.15 μm CMOS with high reliability and performance

Takeuchi, Kiyoshi; Yamamoto, Tetsuya; Tanabe, A.; Matsuki, Takeo; Kunio, Takeshi; Fukuma, M.; Nakajima, Kanako; Aizaki, H.; Miyamoto, Hiroyuki; Ikawa, Eiji

doi:10.1109/iedm.1993.347259

Cited by 9 publications

(4 citation statements)

References 3 publications

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“…This is similar to that discussed by [172]. Furthermore, it was said that Vc s tr = V Dstr will the worst case degradation condition for deep submicron devices having thin gate oxide in the gate direct tunneling regime [173,174,175].…”

Section: Core Transistorssupporting

confidence: 73%

Effects of small gate length, gate width and s/d overhang on mosfets isolated by STI technology

See¹

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Section: Core Transistorssupporting

confidence: 73%

Effects of small gate length, gate width and s/d overhang on mosfets isolated by STI technology

See¹

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“…In short channel NMOSFETs, lifetime at becomes shorter than that at [17]- [19]. This means that the CHE degradation caused by the hot electron injection alone becomes more severe than that caused by the hot carrier recombination.…”

Section: A Modeling Of Channel Hot Electron Lifetimementioning

confidence: 95%

“…On the other hand, it has been reported that worst case gate voltage condition changes from the traditional condition to the channel hot electron (CHE) condition at in short channel NMOSFETs [17]- [19]. Modeling of the CHE degradation is also needed.…”

Section: Introductionmentioning

confidence: 98%

A Drain Avalanche Hot Carrier Lifetime Model for n- and p-Channel MOSFETs

Koike

Tatsuuma

2004

IEEE Trans. Device Mater. Relib.

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A simple and physical drain avalanche hot carrier lifetime model has been proposed. The model is based on a mechanism of interface trap generation caused by recombination of hot electrons and hot holes. The lifetime is modeled as. The formula is different from the conventional -sub model in that the exponent of is 2, which results from the assumed mechanism of the two-carrier recombination. It is shown that the mechanism gives a physical basis of the empirical -sub model for NMOSFETs. The proposed model has been validated experimentally both for NMOSFETs and for PMOSFETs. Model parameters extracted from experimental data show that carrier critical energies for creating damage are lower than the interface potential barriers. It is supposed that oxide band edge tailing enables low-energy carriers to create the damage. The channel hot electron condition becomes the worst case in short channel NMOSFETs, because gate voltage dependence of the maximum channel electric field decreases.

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“…16 Programming current (I g e ) measured in three different electron injection schemes for N-channel transistors fabricated by 0.14-μm technology (cell B). The drawn channel dimension (W/L) = 10/0.176 μm/μm and the tunnel-oxide thickness t ox = 8.1 nm.…”

mentioning

confidence: 99%

Impact of channel engineering on hot-electron injection in the deep-submicrometer flash memory cell

Zhang¹

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First and foremost, I would like to express my deepest gratitude to my project supervisor, Dr. Ang Diing Shenp, for his patient guidance, invaluable advice, persistent support and encouragement throughout the entire course of the project, without which the completion of the project would not have been possible. His devotion and determination towards scientific research have greatly inspired me to strive not only for the research project but also for my professional career in future. I also wish to offer my sincere thanks to Mr. Tan Kok Tong, the project co-supervisor in Systems on Silicon Manufacturing Company (SSMC) Pte. Ltd, for giving me this great opportunity to pursue a higher degree in the field of advanced semiconductor technology. Special appreciation goes to my SSMC mentor, Mr. Kuan Hing Poh, who had given me very helpful suggestions and willingly shared his knowledge on Flash memory technology. I am also grateful to Mr. Glen Foo and Mr. Derek Sim, for the enlightening discussion we had as well as their kindness in sharing the testing machine with me. In addition, I am indebted to my family members, especially my parents and grandparents, for their continuous love and moral support all along. I also want to take this opportunity to thank my dearest Tony for his great understanding as well as encouragement during the course of the project. Last but not least, I would like to extent my sincere thanks to all my colleagues in the Sensors & Actuators Lab II (NTU), as well as the engineers in the Section of Failure Analysis and Reliability (SSMC), for their help in making this project successful. Finally, I am grateful to SSMC for providing the research scholarship and the test devices used in this research project.

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0.15 μm CMOS with high reliability and performance

Cited by 9 publications

References 3 publications

Effects of small gate length, gate width and s/d overhang on mosfets isolated by STI technology

Effects of small gate length, gate width and s/d overhang on mosfets isolated by STI technology

A Drain Avalanche Hot Carrier Lifetime Model for n- and p-Channel MOSFETs

Impact of channel engineering on hot-electron injection in the deep-submicrometer flash memory cell

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