0.18-µm CMOS driver optimization for maximum data rate under power and area constraints

Abstract

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A Sub-pJ/Bit, Low-ER Mach–Zehnder-Based Transmitter for Chip-to-Chip Optical Interconnects

“…The design methodology proposed in [24] is applied here to find both the ideal number N of inverter stages and the transistors sizes of the driver. Such methodology is built on the logical effort method.…”

“…According to [24], the driver optimization leads to a tradeoff between speed, energy efficiency, and area. To highlight these relationships, equations are presented hereafter to estimate the DR limitation and power consumption from the inverter sizes.…”

“…considering the sum of the modulator and driver parasitic capacitance [24]. From experimental data, one may define E avg = P avg /DR using the average power consumption.…”

“…With respects to the targeted driver's specifications, i.e., a 300 fF modulator load, DR = 20 Gbps , and sub-pJ/bit consumption, 55-nm CMOS technology from ST is chosen. By applying the design methodology described in [24], the driver is designed with four inverter stages of increasing dimensions. The ratio between the inverter sizes is set to 2.3 and the widths of the last NMOS and PMOS transistors are 39 and 78 µm, respectively.…”