2015
DOI: 10.1016/j.solmat.2015.02.004
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0.4% absolute efficiency increase for inline-diffused screen-printed multicrystalline silicon wafer solar cells by non-acidic deep emitter etch-back

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Cited by 10 publications
(5 citation statements)
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“…Using a Centrotherm furnace, the wafers were n + diffused by heating to peak temperature of 870 °C to achieve 40–50 Ω/sq sheet resistance ( R sq ). The ‘SERIS etch’ was performed on diffused wafers for 3 minutes to increase R sq to a targeted value of R sq ∼ 80–90 Ω/sq. With an inline plasma enhanced chemical vapour deposition (PECVD) system (Roth &Rau, SiNA‐XS), an antireflection and passivation layer of amorphous silicon nitride (SiN x ) with thickness of 70 nm and refractive index of 2.05 (at 633 nm) was deposited at a substrate temperature of 400 °C.…”
Section: Methodsmentioning
confidence: 99%
“…Using a Centrotherm furnace, the wafers were n + diffused by heating to peak temperature of 870 °C to achieve 40–50 Ω/sq sheet resistance ( R sq ). The ‘SERIS etch’ was performed on diffused wafers for 3 minutes to increase R sq to a targeted value of R sq ∼ 80–90 Ω/sq. With an inline plasma enhanced chemical vapour deposition (PECVD) system (Roth &Rau, SiNA‐XS), an antireflection and passivation layer of amorphous silicon nitride (SiN x ) with thickness of 70 nm and refractive index of 2.05 (at 633 nm) was deposited at a substrate temperature of 400 °C.…”
Section: Methodsmentioning
confidence: 99%
“…28 Thus there are no reports available for the application of acid-based heavy or deep etch-back processes. However, our earlier work [19][20][21] for inline-diffused multi-Si wafers already showed that the 'SERIS etch' is able to maintain the integrity of the textured surfaces, even for deep etch-backs up to DR sq $ 30 U sq À1 . 19 In the present work we have extended the 'SERIS etch' etch-back range to DR sq of $40 U sq À1 , and studied changes in WAR values for the as-diffused and etch-back emitters.…”
Section: Emitter Parametersmentioning
confidence: 99%
“…Normally the reectance of iso-textured multi-Si surfaces varies more along the complete wafer surface as compared to alkaline textured mono-Si wafers. 21 So we have selected identical location on multi-Si wafers for all the emitters, so that during reectance measurement, error in WAR values can be minimised to some extent. From Fig.…”
Section: Emitter Parametersmentioning
confidence: 99%
“…3a . If there is no annealing or the annealing is insufficient, the barrier height and the serial resistance would become larger [ 18 20 ], which could severely degrade the performance of solar cell. On the other hand, if the annealing is overdone, Ag will easily penetrate through SiO 2 and into the emitter zone or even into the PN junction, then the whole device would be ruined.…”
Section: Resultsmentioning
confidence: 99%