2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) 2013
DOI: 10.1109/s3s.2013.6716578
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0.42-to-1.20V read assist circuit for SRAMs in CMOS 65nm

Fady Abouzeid
1
,
Sylvain Clerc
2
,
Bertrand Pelloux-Prayer
3
et al.
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Sub-threshold 10T SRAM bit cell with read/write XY selection

Féki
1
,
Allard
2
,
Turgis
3
et al. 2015
Solid-State Electronics
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Sub-threshold 10T SRAM bit cell with read/write XY selection

Féki
1
,
Allard
2
,
Turgis
3
et al. 2015
Solid-State Electronics
18
0
9
0
View full textAdd to dashboardCite

Optimizing VMIN of ROM Arrays Without Loss of Noise Margin

Chakraborty
1
,
Walker
2
2015
Proceedings of the 25th Edition on Great Lakes Symposium on VLSI
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