0.5 mu m BiCMOS standard-cell macros including 0.5 W 3 ns register file and 0.6 W 5 ns 32 kB cache

Kara, H.; Sakurai, Takayasu; Nagamatsu, T.; Kobayashi, Sachiko; Seta, K.; Momose, H.S.; Niitsu, Y.; Miyakawa, H.; Kuroda, Tadahiro; Matsuda, K.; Watanabe, Yoshihiro; Sano, Fumihiko; Chiba, A.

doi:10.1109/isscc.1992.200403

Cited by 1 publication

(3 citation statements)

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“…As an example, TABLE 111 lists a speed comparison between 3.3V 0.5pm BiCMOS and CMOS macrocells [3]. Big speed advantage of the BiCMOS macros come from bipolar specific circuits like ECL comparators and ECL hit logic in a cache macro, whose circuit diagram is shown in Fig.…”

Section: Bicmos Macro Examdle and Future Trendmentioning

confidence: 99%

“…Since ECL-like reduced swing operation is the key to the high speed in these macros, an ECL+CMOS type BiCMOS [3,7,8,9] seems promising. In the ECL+CMOS type BiCMOS, the communication between ECL and CMOS is important.…”

Section: Bicmos Macro Examdle and Future Trendmentioning

confidence: 99%

“…In the ECL+CMOS type BiCMOS, the communication between ECL and CMOS is important. One proposal is a direct coupled ECL-CMOS [3] as shown in Fig.13. Supplying 2V for CMOS, the CMOS inverter delay (F-1) is 13Ops.…”

Section: Bicmos Macro Examdle and Future Trendmentioning

confidence: 99%

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High-speed/high-density logic circuit design

Sakurai

1993 International Symposium on VLSI Technology, Systems, and Applications Proceedings of Technical Papers

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Problems and possible solutions to implement high-speed logic VLSI's with advanced CMOS I BiCMOS technology are discussed. The technology trend is summarized first in conjunction with its impact on the circuit designs. The paper covers BiCMOS circuit designs and other basic high-speed circuit techniques including gate sizing, dynamic I reduced swing circuits, interconnect I clock delay, and on-chip memory. These items are discussed with possible scaling effects. Future highspeed design should cope with 1 o w -V~~ related problems including threshold voltage scaling, interconnection delay problems including clock distribution problems, power and noise. These constraints get severer as scaling advances.

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Section: Bicmos Macro Examdle and Future Trendmentioning

confidence: 99%

Section: Bicmos Macro Examdle and Future Trendmentioning

confidence: 99%