0.5 μm AlGaAs/GaAs HMESFET technology for digital VLSI products

Design of a 32 b monolithic microprocessor based on GaAs HMESFET technology

“…Based on the same layout one can evaluate the next generation F-RISC/I performance by simulating the critical paths. Using the experimental process as a benchmark, Rockwell's baseline 0.7 and 0.5 m HMESFET process improves the K value by a factor of 1.36 and 1.85, respectively, while the interconnect capacitance per unit length remains the same and the wire lengths scale according to published design rules [2]. The critical path simulations were performed with scaled interconnect capacitance to predict an upper bound for the performance of F-RISC/I implementations.…”

“…Recent advances in GaAs Heterojunction MESFET (HMESFET) technology have led to gate delays below 100 ps [1] and higher integration levels, reaching VLSI complexity and, thereby, allowing the implementation of a 32 b GaAs RISC on a single chip [2]. However, integration levels are still very low compared to CMOS and do not allow the inclusion of sufficiently large caches on the chip.…”