0.5V 4.8 pJ/SOP 0.93\mu \mathrm{W}$ Leakage/core Neuromorphic Processor with Asynchronous NoC and Reconfigurable LIF Neuron

Energy efficient neuromorphic computing circuit and architecture design

“…Furthermore, it makes up for the shortcomings of the pipeline structure. When the input spike rate is 50% and 10%, the processing speed of the neuron core is significantly increased by 1.9× and [8,9]. It demonstrates that the proposed pipeline circuit can significantly reduce the processing time of NCU under various spike injection rates.…”

“…The synapse processing speed affects the performance and energy efficiency of the SNN hardware. Previous works [5,6,9], and [8] used synchronous circuits to implement the neuron computation unit, and each synapse operation required more than one clock cycle. Besides, using a finite state machine [8] and [9] reduces the flexibility of the neuron computing operation.…”

“…Previous works [5,6,9], and [8] used synchronous circuits to implement the neuron computation unit, and each synapse operation required more than one clock cycle. Besides, using a finite state machine [8] and [9] reduces the flexibility of the neuron computing operation. Therefore, as tasks increase, the neuron computing speed will decrease further.…”

“…In order to verify the impact of the proposed pipeline architecture on the synapse processing speed of NCU, this work compares the proposed NCU with other synchronous designs [5,6,8,9,47]. increases the synapse processing speed by 1.4× as compared with the TrueNorth chip.…”

“…Thus, skipping axons that have no input spike can effectively increase the processing speed of the neuron core. The first version of SNN hardware (Novena 1) [8,9] uses a finite state machine to process the input spike. However, its disadvantage is that the neuron core needs to use many clock cycles to process those axons without input spikes.…”