0.6 µm CMOS, 622/155 Mbit/s ATM-SDH/SONETframer IC

Abstract

Framer ASIC which implements the SDH/SONET based Transmission Convergence (TC) sublayer of the B-ISDN reference model, has been fabricated. The FRAMER chip is suitable for 622.08 or 155.52 Mbit/s line rates. It incorporates 491K transistors, consumes 2W of power and has been implemented in 0.6µm CMOS technology.