0.6mW 6.3 GHz 40nm CMOS divide‐by‐2/3 prescaler using heterodyne phase‐locking technique

Abstract

A dual-modulus prescaler based on the heterodyne phase-locking technique is presented. Different to the conventional LC tank based phaselocked loop, by directly locking at two injection-locked ring oscillators simultaneously, a dual-modulus operation is achieved while a widerange operating, significantly reduced settling time and low power consumption are achieved. Implemented in a standard 40nm CMOS process, the proposed divide-by-2 and 3 dual-modulus prescaler achieves an operating frequency of 6.3GHz with a measured power consumption of 0.6mW from a 1.1V supply.Introduction: The dual-modulus prescaler is widely utilised in the frequency divider for phase-locked frequency synthesisers where programmable divisions are needed. It is usually implemented with a digital circuit which consumes quite a large power at the gigahertz range [1]. The injection-locked frequency divider (ILFD), which achieves a higher operating frequency with lower power consumption, is a promising solution for high-speed applications [2,3]. Nevertheless, the ILFD is conventionally of a fixed division ratio, which limits its usage in today's VLSI systems. Several ILFDs have been proposed recently to overcome this issue [3]. For example, by proper sizing of transistors in the oscillator core, two self-resonant frequencies at dual-modulus operations are designed to host dual division ratios [3]. Such a solution is quite simple but not robust against potential process variations since the switching of self-resonant frequency depends heavily on the transistor's parasitic capacitance. The heterodyne phase-locking technique, as proposed in [4], is able to provide flexible division ratios. However, it has a large silicon area and long settling time. In this Letter, a new heterodyne phase-locking divider is proposed. A good compromise among robustness, operating range, power consumption, and silicon area is achieved.

19.1 GHz 18 mW divide‐by‐3 heterodyne injection locking frequency divider in 0.18 µm CMOS technology

“…This makes it less attractive in real applications. To solve these issues, a heterodyne phase‐locking divider based on the injection‐locking oscillator (ILO) instead of the voltage‐controlled oscillator (VCO) is implemented in [4]. In that design, the oscillator is locked into the output harmonic of the mixer, which is much faster than that of a VCO.…”

“…The heterodyne phase-locking technique is proposed in [3] to obtain larger division ratio and higher operating frequency. Nevertheless, the work is not optimised with fast settling and small silicon area [4]. In this Letter, a new divide-by-3 divider based on heterodyne injection-locking technique with efficiency and locking range enhanced LC oscillator, maintaining a good balance among major design considerations, is proposed and silicon verified.…”

“…Proposed work: The proposed work is based on the heterodyne injection locking in [4] instead of phase locking in [3]. To make a fair comparison with literature work, a divide-by-3, which is of much narrow working range compared with divide-by-2, is proposed as shown in Fig.…”

“…To achieve a high working frequency above GHz range, the LC tank based ILO is implemented instead of the ring oscillator in [4]. The input signal of the ILO is down-converted through three mixers, which is quite weak even when a buffer is included.…”

A low-power high-speed true single-phase clock-based divide-by-2/3 prescaler

“…They are used only for high frequency where other topologies cannot operate. Injection-locked prescalers can achieve a high operating frequency with lower power consumption [3,4]. However, they have a small input frequency locking range and limited output swing.…”