0.8&amp;amp;#181;m Bi-CMOS technology with high f&lt;inf&gt;T&lt;/inf&gt;ion-implanted emitter bipolar transistor

Sasaki, Gen; Unno, Y.; Niitsu, Y.; Norishima, M.; Sugimoto, Yasuhiro; Kanzaki, K.

doi:10.1109/iedm.1987.191339

Cited by 12 publications

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“…Npn bipolar transistors were fabricated by a 0.8pm ion-implanted emitter BiCMOS process [4]. In most of the cases, the emitter size was 4 x 2.2 pm2.…”

Section: Methodsmentioning

confidence: 99%

Temperature dependence of emitter-base reverse stress degradation and its mechanism analyzed by MOS structures

Momose

Nitsu

Maeguchi

Proceedings of the Bipolar Circuits and Technology Meeting

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Temperature dependence of emitter-base reverse stress degradation was studied. Different degradation modes were observed between high and low reverse stress current conditions. It was found that, the degradation is the largest around 50°C. The mechanisms of the degradation and its recovery were also investigated, using MOS structures and simulation. By the MOSFET evaluation, it was confirmed that electron trapping and interface state generation occurs during the stress. By the simulation, it was also confirmed that the degradation is caused mainly by the generated interface states in the oxide near the emitter-base junction. INTRODUCTIONRecently, bipolar transistor degradation under emitterbase reverse bias stress has been studied intensively [l-31. However, there have been very few reports about its temperature dependence in its operating range. This paper describes the temperature dependence of the degradation in detail. In addition, its degradation and recovery mechanisms were also investigated by MOSFET structures and two-dimensional simulations.

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“…Npn bipolar transistors were fabricated by a 0.8pm ion-implanted emitter BiCMOS process [4]. In most of the cases, the emitter size was 4 x 2.2 pm2.…”

Section: Methodsmentioning

confidence: 99%

Temperature dependence of emitter-base reverse stress degradation and its mechanism analyzed by MOS structures

Momose

Nitsu

Maeguchi

Proceedings of the Bipolar Circuits and Technology Meeting

Self Cite

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“…In addition, a full swing of 1.5V at the output of the BiCMOS dynamic logic gate can be obtained. In order to show the effectiveness of the 1.5V fullswing BiCMOS dynamic logic gate circuit, a test chip including a two-stage BiCMOS dynamic logic gate circuit with the BiPMOS pull-down structure has been designed based on a l p m BiCMOS technology [9]. Fig.…”

Section: The Bipmos Pull-down Structurementioning

confidence: 99%

Device-level analysis of a BiPMOS pull-down device structure for low-voltage dynamic BiCMOS VLSI

Kuo

Lou

et al.

Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94

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This paper presents a device-level analysis of a B i P M O S pull-down structure for low-voltage dynamic BiCMOS logic gate circuit suitable f o r VLSI using subquarter-micron BiCMOS technology. Thanks t o the B i P M O S pull-down structure, despite the slow t u m -08 of the bipolar device, the 1.5V full-swing BiCMOS dynamic logic gate circuit shows a more than 1.8 times improvement in speed as compared to the C M O S static one.

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Integrated Silicon Photodetectors

Zimmermann

2004

Silicon Optoelectronic Integrated Circuits

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0.8&#181;m Bi-CMOS technology with high f<inf>T</inf>ion-implanted emitter bipolar transistor

Cited by 12 publications

References 0 publications

Temperature dependence of emitter-base reverse stress degradation and its mechanism analyzed by MOS structures

Temperature dependence of emitter-base reverse stress degradation and its mechanism analyzed by MOS structures

Device-level analysis of a BiPMOS pull-down device structure for low-voltage dynamic BiCMOS VLSI

Integrated Silicon Photodetectors

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