0.9 V DSP blocks: a 15 ns 4 K SRAM and a 45 ns 16-bit multiply/accumulator

Hallmark, Jerry; Shurboff, C.; Ooms, B.; Lucero, R.; Abrokwah, J.; Huang, Jane-Hwa

doi:10.1109/gaas.1994.636918

Cited by 10 publications

(4 citation statements)

References 7 publications

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“…'Fast' refers to memories explicitly designed for high speed, 'low-V' refers to memories designed at a voltage significantly lower than the norm in that category and at that gate length, comp refers to complementary. [127,128].…”

Section: Modementioning

confidence: 99%

Tunnelling-based SRAM

Wagt

1999

Nanotechnology

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This paper describes the use of low-current-density tunnelling devices to obtain dense low-power (sub-100 nW/bit) compound semiconductor static random access memory (SRAM); this cell power is over two orders of magnitude lower than the best previously demonstrated in III-V materials. This same circuit topology promises orders of magnitude reduction in static power dissipation for silicon memories, assuming a suitable Si-based negative differential resistance device, at sub-pA current levels, is developed. The concept of low-standby-power tunnelling-based SRAM (TSRAM) is presented in the context of a scaling theory for all memories and a comparison is given across technologies. Experimental results for a 50 nW TSRAM gain cell using ultralow current density (~1 A cm-2) resonant tunnelling diodes and low-leakage heterostructure field-effect transistors are discussed. We describe a one-transistor TSRAM cell, verify its operation, and discuss merits of TSRAM relative to other memory types. Silicon TSRAM standby power is projected to be lower than that of conventional-style silicon SRAM or DRAM.

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Section: Modementioning

confidence: 99%

Tunnelling-based SRAM

Wagt

1999

Nanotechnology

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“…Two key parameters of concern in complementary heterostructure FET devices are gate leakage and sub-threshold drain-source leakage [7,10], which determine the stand-by power dissipation of complementary circuits. Unlike Si CMOS, which has an SiO 2 gate insulator, the CGaAs gate is a Schottky diode to AlGaAs.…”

Section: Complementary Gaas Technology Descriptionmentioning

confidence: 99%

Overview of complementary GaAs technology for high-speed VLSI circuits

Brown

Bernhardt

LaMacchia

et al. 1998

IEEE Trans. VLSI Syst.

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A self-aligned complementary GaAs (CGaAs TM) technology developed at Motorola for low-power, portable, digital and mixed-mode circuits is being extended to address highspeed VLSI circuit applications. The process supports full complementary, unipolar (pseudo-DCFL), source-coupled, and dynamic (domino) logic families. Though this technology is not yet mature, it is years ahead of CMOS in terms of fast gate delays at low power supply voltages. Complementary circuits operating at 0.9V have demonstrated power-delay products of 0.01µW/MHz/gate. Propagation delays of unipolar circuits are as low as 25 ps. Logic families can be mixed on a chip to trade power for delay. CGaAs is being evaluated for VLSI applications through the design of a PowerPC TM-architecture microprocessor. This paper touches on the major aspects of the project, process technology, circuit design, packaging, architecture, CAD tools and software, with an emphasis on application of the CGaAs technology.

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“…The operating speed and power per gate for each style is shown in Figures 5 & 6. All of these styles may be used together on the standard CGaAs process and circuits can operate over a range from DC to greater than 5 Gb/s, with world class speed-power in each regime [2]. This architectural versatility provides many of the advantages of BiCMOS, but with a much simpler process.…”

Section: Architechture Versatilitymentioning

confidence: 99%

“…The SCFL circuits operated at -4 Volts while the complementary blocks used a -1.2V supply. Further testing showed that {he S C E supply could be reduced to -2.51V while maintaining operation at lGHz and this reduced the speed-power to 0.16 pU'/MHz/gate [2].…”

Section: B Mixed Digital Designsmentioning

confidence: 99%

Complementary GaAs (CGaAs) technology and applications

Hallmark

Abrokwah

Bernhardt³

et al.

Proceedings of ISSE'95 - International Symposium on Signals, Systems and Electronics

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A self aligned complementary GaAs (CGaAsTh4) technology has been developed for low-power, high-speed digital and mixed-mode applications. A single process flow has been used to build low-voltage, low-power, full-complementary digital circuits at 200MHz, high-speed SCFL digital circuits at SGHz, RF MMIC and power circuits (900MHz), and combinatioms of these. Complementary digital circuits have demonstrated speed-power performance of 0.1pWIMHzJgate at 0.9V. A mixed SCFll Complementary signal processor operated at > lGHz with a speed-power performance of 0.16pWIMHdgate.

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0.9 V DSP blocks: a 15 ns 4 K SRAM and a 45 ns 16-bit multiply/accumulator

Cited by 10 publications

References 7 publications

Tunnelling-based SRAM

Tunnelling-based SRAM

Overview of complementary GaAs technology for high-speed VLSI circuits

Complementary GaAs (CGaAs) technology and applications

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