1×16 optical packet switch sub-system with a monolithically integrated InP optical switch

Abstract

Document VersionPublisher's PDF, also known as Version of Record (includes final page, issue and volume numbers)Please check the document version of this publication:• A submitted manuscript is the author's version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website.• The final author version and the galley proof are versions of the publication after peer review.• The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication General rightsCopyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research.• You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal ? Take down policyIf you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim. Abstract: We demonstrate a 1x16 optical packet switch sub-system for 160 Gbps RZ-OOK and 12 x 10 Gbps multi-wavelength DPSK packets. We show error-free operation with maximum penalties of 0.7 dB for 160 Gbps RZ-OOK and 0.6 dB for multi-wavelength DPSK packets.

Scaling Low-Latency Optical Packet Switches to a Thousand Ports

“…(3) to compute the upper bound of the average system latency (latency UB ). Hence, the mean latency UB can be computed, considering that latency UB = RTT + t switch + P RetrMax latency UB (7) or Figure 7 shows the upper bound of the average system latency as a function of the port count, considering a switch based on Beneš and Spanke architectures according to Eq. (8), and for load = 1.…”

“…The MOTOR device [5] is an 8 × 8 monolithically InP integrated optical switch based on tunable wavelength converters. In [6,7], an InP-based integrated 1 × 16 optical switch has been presented. It can simultaneously handle both on-off keying and differential phase-shift keying modulated data packets.…”

Scaling photonic packet switches to a large number of ports

“…An integrated 1 x 100 has recently been demonstrated [5]. An integrated 1x16 switch that can switch change state within 5 ns in a full packet switched system has also been demonstrated [12]. Within these 5 ns, a packet header was recognized and processed to generate control signals for the switch.…”