1.2–2.8-GHz 32.4-dBm Digital Power Amplifier With Balance-Compensated Matching Network

Abstract

In this letter, a wideband watt-level digital power amplifier (DPA) with a balance-compensated matching network is proposed for polar transmitters. The balance response of the differential to the single-ended transformer is enhanced by a series-loaded compensation capacitor, which leads to the improvement of the DPA efficiency. To verify the mechanisms, a prototype DPA is fabricated in conventional 40-nm CMOS technology. The proposed DPA operates over 1.2-2.8 GHz and exhibits a peak output power of 32.4 dBm at 2 GHz and a peak drain efficiency of 53.8% at 1.8 GHz. It supports 50-MHz 64-quadratic-amplitude modulation (QAM) with average output power (P avg) of 25.37 dBm, error vector magnitude (EVM) of −26.97 dB, adjacent channel power ratio (ACPR) of −29.61 dBc, and 10-MHz 1024-QAM with P avg of 22.14 dBm, EVM of −35.75 dB, and ACPR of −35.37 dBc, respectively.

A State-of-the-Art Review on CMOS Radio Frequency Power Amplifiers for Wireless Communication Systems

“… PAE across output power for the proposed efficiency enhancement techniques [ 55 , 58 , 60 , 61 , 62 , 63 , 64 , 65 , 66 , 67 , 72 , 73 , 74 , 77 , 78 , 79 , 80 , 85 , 86 , 87 , 89 , 90 , 91 , 92 , 99 , 100 , 101 , 102 , 103 , 104 ]. …”

“…T. Wang et al (2021) presented an on-chip transformer-based digital CMOS PA in which the transformer acted as a balance-compensated matching network [65]. A seriesloaded compensation capacitor was utilized to enhance the balance response of the transformer, which improved the efficiency of the CMOS PA.…”