1.2-V Low-Power Multi-Mode DAC+Filter Blocks for Reconfigurable (WLAN/UMTS, WLAN/Bluetooth) Transmitters

Ghittori, N.; Vigna, A.; Malcovati, P.; D'Amico, S.; Basçhirotto, A.

doi:10.1109/jssc.2006.880602

Cited by 37 publications

(20 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The topology of this implementation uses cascoding and is not straightforward to apply in low-power 65 nm CMOS with 1.2 V supply. For comparison, recent voltage-mode filters are presented in [9,10] and [11]. Due to the different mode of operation, voltage-mode and current-mode filters are difficult to compare.…”

Section: Resultsmentioning

confidence: 99%

A current-mode continuous-time filter for software defined radio solutions

Uhrmann

Zimmermann

2008

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

A 3rd-order continuous-time current-mode filter in 65 nm CMOS technology is presented. The filter has a switchable cut-off frequency between 1.1 and 4.4 MHz and is designed for software defined radio on chip (SDR) solutions. An innovative extension to structures in literature is proposed, that allows saving chip area at low cut-off frequencies. Furthermore a mathematical estimation is presented to show the usability of the structure. The realized chip has an active area of 350 lm 9 220 lm and consumes 12.3 mW at 1.2 V. The dynamic range for a bandwidth of 1.1 MHz is 77.2 dB, the in-band output current noise is 31:16 pA= ffiffiffiffiffiffi Hz p and the IIP3 is 1.8 mA p .

show abstract

Section: Resultsmentioning

confidence: 99%

A current-mode continuous-time filter for software defined radio solutions

Uhrmann

Zimmermann

2008

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

show abstract

“…To compare the proposed architecture with a typical one, operating at 100 MHz [3], we estimated the performance required by an interpolation filter from 100 MHz to 600 MHz, i.e. with interpolation factor equal to 6.…”

Section: Digital Interpolation Filtermentioning

confidence: 99%

“…This trade-off is presently optimized with a DAC data-rate about 8-10 times the signal bandwidth and a 4-6th order analog reconstruction filter. For instance, in the case of the WLAN IEEE 802.11a standard (whose signal bandwidth is equal to 10 MHz), the DAC data-rate is around 100 MHz [1][2][3].…”

Section: Introductionmentioning

confidence: 99%

An IEEE 802.11 and 802.16 WLAN Wireless Transmitter Baseband Architecture with a 1.2-V, 600-MS/s, 2.4-mW DAC

Ghittori

Vigna

Malcovati

et al. 2008

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

In this paper, we propose a transmitter baseband architecture for the present and up-coming WLAN applications (IEEE 802.11a/g, 802.11n, 802.16), based on a 600-MS/s current-steering DAC with a passive output load, to perform the baseband signal processing, avoiding the use of any active analog reconstruction filter. The DAC, fabricated in a 0.13-lm CMOS technology, consumes 2.4 mW from a 1.2-V single supply voltage. The DAC exhibits 68 dB of SFDR at full-scale for a 12-MHz input signal frequency and 9.7 bits of full-scale dynamic range in the bandwith from dc to 10 MHz.

show abstract

“…These baseband signals are then shifted to radio frequency (RF) by two quadrature mixers, and summed up to obtain the final waveform to be transmitted at the antenna, after the amplification provided by the power amplifier (PA) [2]. The baseband sections of such telecom standard transmitters typically consist of cascading of a digital-to-analog con- verter (DAC), receiving the digital signal processor (DSP) bit-stream, and an analog reconstruction filter, which has to suppress the DAC spectral images.…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 12-Bit 1-Gsample/s Nyquist Current-Steering DAC in 0.35 µm CMOS for Wireless Transmitter

Aliparast

Bahar²,

Koozehkanani³

et al. 2011

View full text Add to dashboard Cite

The present work deals with 12-bit Nyquist current-steering CMOS digital-to-analog converter (DAC) which is an essential part in baseband section of wireless transmitter circuits. Using oversampling ratio (OSR) for the proposed DAC leads to avoid use of an active analog reconstruction filter. The optimum segmentation (75%) has been used to get the best DNL and reduce glitch energy. This segmentation ratio guarantees the monotonicity. Higher performance is achieved using a new 3-D thermometer decoding method which reduces the area, power consumption and the number of control signals of the digital section. Using two digital channels in parallel, helps reach 1-GSample/s frequency. Simulation results show that the spuriousfree-dynamic-range (SFDR) in Nyquist rate is better than 64 dB for sampling frequency up to 1-GSample/s. The analog voltage supply is 3.3 V while the digital part of the chip operates with only 2.4 V. Total power consumption in Nyquist rate measurement is 144.9 mW. The chip has been processed in a standard 0.35 µm CMOS technology. Active area of chip is 1.37 mm 2 .

show abstract

1.2-V Low-Power Multi-Mode DAC+Filter Blocks for Reconfigurable (WLAN/UMTS, WLAN/Bluetooth) Transmitters

Cited by 37 publications

References 7 publications

A current-mode continuous-time filter for software defined radio solutions

A current-mode continuous-time filter for software defined radio solutions

An IEEE 802.11 and 802.16 WLAN Wireless Transmitter Baseband Architecture with a 1.2-V, 600-MS/s, 2.4-mW DAC

A 12-Bit 1-Gsample/s Nyquist Current-Steering DAC in 0.35 µm CMOS for Wireless Transmitter

Contact Info

Product

Resources

About

1.2-V Low-Power Multi-Mode DAC+Filter Blocks for Reconfigurable (WLAN/UMTS, WLAN/Bluetooth) Transmitters

Cited by 37 publications

References 7 publications

A current-mode continuous-time filter for software defined radio solutions

A current-mode continuous-time filter for software defined radio solutions

An IEEE 802.11 and 802.16 WLAN Wireless Transmitter Baseband Architecture with a 1.2-V, 600-MS/s, 2.4-mW DAC

A 12-Bit 1-Gsample/s Nyquist Current-Steering DAC in 0.35 &#181;m CMOS for Wireless Transmitter

Contact Info

Product

Resources

About

A 12-Bit 1-Gsample/s Nyquist Current-Steering DAC in 0.35 µm CMOS for Wireless Transmitter